675242 event 1719425034 1719605744 <![CDATA[Ph.D. Dissertation Defense - Rakshith Saligram]]> Title:  Cryogenic CMOS Circuits for High Performance Digital Systems

Committee:

Dr. Arijit Raychowdhury, ECE, Chair, Advisor

Dr. Suman Datta, ECE

Dr. Sung-Kyu Lim, ECE

Dr. Muhannad Bakir, ECE

Dr. Yu (Kevin) Cao, UMN

]]> There has been an increasing demand for energy-efficient processors, particularly with the rise of AI, ML, and LLMs. Cryogenic computing, which operates at ultra-low temperatures (-196°C / 77K), offers enhanced performance and energy efficiency due to superior device characteristics such as higher drive current, lower subthreshold slope, ultra-low leakage, and reduced interconnect resistance. This technology opens up new design possibilities at both the circuit and system levels, and revives memory technologies otherwise outdated by technological evolution. In this work, we demonstrate how these improved device and interconnect properties lead to faster, smaller, and lower power systems. We developed in-house cryogenic device models calibrated with experimental data for both transistors and wires, using a 22nm FDSOI process. These robust, scalable models support cryogenic circuit simulation for advanced system design. A matrix multiplication accelerator test chip built in a 40nm CMOS process showed up to 26% energy efficiency improvement at low temperatures. New biasing techniques for dynamic logic circuits were proposed, resulting in a 41% energy reduction for a 64-bit domino logic adder compared to room temperature operation. We also co-optimized a 6T SRAM design, achieving 5.4x lower energy and 1.2x lower delay, and demonstrated a 28nm hybrid 2T gain cell embedded DRAM test chip operating from 4K to 300K, showing significant improvements in energy efficiency, retention time, and refresh rate. Additionally, we conducted a design technology co-optimization of a 64-bit Arm processor, recharacterizing over 12 standard cell libraries across temperatures and voltages. The results showed a more than 4x improvement in energy efficiency at low temperatures. Thermal behavior analysis indicated that cryogenic computing could theoretically allow more chips to be packaged together within a given thermal design power limit. Finally, we analyzed cooling costs, identified key roadblocks, and proposed future research directions.

]]> <![CDATA[]]> https://teams.microsoft.com/l/meetup-join/19%3ameeting_NDU5ZDk4OTYtZDkxYi00Y2VmLWFmZjMtMWM3ZDNkYTg2ZGVi%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%223b2c4af8-bf49-45a1-995c-6f86ad94608e%22%7d 434381 1788 100811 1808