673380 event 1709752569 1709752569 <![CDATA[Ph.D. Dissertation Defense - Yuan-Chun Luo]]> Title:  Design-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-memory Computing and On-Chip Buffers

Committee:

Dr. Shimeng Yu, ECE, Chair, Advisor

Dr. Shaolan Li, ECE

Dr. Asif Khan, ECE

Dr. Azad Naeemi, ECE

Dr. Jae-Sun Seo, Cornell

]]> Ferroelectric memories have been widely investigated for both compute-in-memory (CIM) and buffer memory applications. For CIM, resistive crossbar arrays have been intensively studied, but they suffer from high static power, serious IR drop, and sneak-path issues. To overcome these challenges, ferroelectric “capacitive” crossbar array is proposed in this thesis since the capacitive approach (1) consumes only dynamic power, (2) has no DC sneak paths, (3) avoids IR drop along wires, and (4) has high 3D stacking potential. In this thesis, ferroelectric capacitive crossbar arrays are investigated from device physics, device/array measurement, circuit simulation, to system-level benchmarking, where a cross-layer framework is built to connect the device and circuit non-ideality to system-level metrics. On the other hand, ferroelectric non-volatile memories as buffer memories will also be investigated. More specifically, 1T1F FeRAM is investigated for its performance from 4K to 400K; 2T1F FeRAM is investigated for its ultra-compact and low-power characteristics compared to 1T1F FeRAM; An endurance-aware compiler is proposed to estimate and solve the endurance issues of the FeRAM; Ferroelectric non-volatile SRAM is investigated due to its zero-leakage and instant-on advantages for low-active-rate edge devices.

]]> <![CDATA[]]> https://teams.microsoft.com/l/meetup-join/19%3ameeting_NDc0NjZhOGMtOGU1Zi00ZWVkLTkzMTYtZDY0N2E5NmM0OTFi%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%22af6bd054-9ec0-4b25-b0ec-a34b37b44713%22%7d 434381 1788 100811 1808