672960 event 1707950139 1707950139 <![CDATA[Ph.D. Dissertation Defense - Anni Lu]]> Title:  Algorithm-Hardware Co-design for Deep Learning and Probabilistic Computing with Compute-in-Memory Accelerators

Committee:

Dr. Shimeng Yu, ECE, Advisor

Dr. Saibal Mukhopadhyay, ECE

Dr. Callie Hao, ECE

Dr. Xinyu Bao, TSMC

Dr. Haitong Li, Purdue

]]> Compute-in-memory (CIM) is a promising paradigm for hardware accelerators of deep learning and probabilistic computing due to its high energy efficiency. In this thesis, algorithm-hardware co-optimizations of CIM are explored across diverse models and applications. First, the integrated benchmark framework “NeuroSim” for CIM accelerators is validated with actual silicon data and calibrated with adjustment factors. Based on this simulator, the CIM architectures under on-chip resource constraints are explored for DNN, addressing the challenge of accommodating large-scale models on area-limited CIM chips, and the reconfiguration of deploying different models on prefabricated CIM chips with fixed hardware resources. The CIM scheme is further extended to probabilistic computing by harnessing the intrinsic memory stochasticity. A novel CIM accelerator for Bayesian neural network is proposed to generate Gaussian distributed weights using the probabilistic switching of spin-orbit torque magnetic RAM (SOT-MRAM) in weak programming. The inherent memory noise is also utilized for scalable and clustered in-memory annealers to solve NP-hard combinatorial optimization problems. An analog CIM annealer using temporal variation of charge-trap FinFET and a digital CIM annealer using process variation of SRAM are proposed.

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