The paper, “Worst-Case Eye Analysis of High-Speed Channels Based on Bayesian Optimization,” was authored by four researchers from Georgia Tech: Madhavan Swaminathan (John Pippin Chair and director of the 3D Systems Packaging Research Center), Sung Kyu Lim (Motorola Solutions Foundation Professor), Majid Ahadi Dolatsara (former Ph.D. candidate currently at Keysight Technologies) and Jinwoo Kim (Ph.D. candidate), and two researchers from IBM: Wiren Dale Becker and Jose Ale Hejase.

With the exponential increase of bitrate in recent years, it has become considerably harder to avoid communication failure when a signal passes through a high-speed channel. Therefore, designers rely on rigorous modeling and simulation in the early stages of design of high-speed channels to predict the jitter and noise. A common analysis to evaluate the quality of the signal is the eye diagram analysis.

In the award-winning article, an optimization-based algorithm for quick evaluation of the eye diagram, dubbed worst-eye analysis, is suggested. Traditionally, eye diagram analysis is performed using a lengthy transient simulation, which can be prohibitive. The team’s proposed approach focuses on the inter-symbol interference since its effect can span over many symbols and include crosstalk (unwanted signals in a communication channel), making it challenging to model.

The new algorithm calculates the data patterns leading to the lowest voltage corresponding to a high symbol, the highest voltage corresponding to a low symbol, and the times of minimum and maximum level crossing points. Then, eye height (EH), eye width (EW), and the worst-case eye opening are estimated using these points. To reduce complexity, the proposed approach includes a mapping algorithm that exploits the Gray code — an ordering of the binary numeral system such that two successive values differ in only one bit.

Numerical results from the team’s analysis showed that the worst-eye proposed approach can accurately find the EW and EH with up to 47 times speedup, and the worst-case eye opening with up to 23 times speedup, when compared with the lengthy transient simulation.

The work was supported in part by the DARPA CHIPS Project under Award N00014-17-1-2950, and in part by the National Science Foundation under Grant CNS 16-24731—Center for Advanced Electronics through Machine Learning and its industry members.

The award will be presented to the team at the annual IEEE EMC+SIPI Symposium in Spokane, Wash. this August.