Committee:

Dr. Sung-Kyu Lim, ECE, Chair, Advisor

Dr. Shimeng Yu, ECE

Dr. Tushar Krishna, ECE

Dr. Madhavan Swaminathan, ECE

Dr. Hyesoon Kim, CoC

Abstract: This dissertation explores various techniques for the electronic design automation (EDA) of integrated circuits (IC) with high-performance and reliability features. We propose novel architectures, machine learning techniques, and physical design methodologies to improve the state-of-the-art technology. In the first theme, we conceive a new die stacking architecture for 3D memory cubes targeting space applications, complemented with custom radiation-hardened-by-design logic controllers. In the second theme, we explore machine learning to improve the implementation flow of a large field-programmable gate array (FPGA) emulation system and help tune the many knobs of a very-large-scale integration (VLSI) placement engine. Finally, for the third theme, we present a power, performance, area, and cost (PPAC) analysis of large-scale 3D IC processor designs, motivating our development of a new hierarchical 3D EDA flow focusing on a more holistic silicon area utilization.