{"649232":{"#nid":"649232","#data":{"type":"news","title":"ICSRL Team Wins ISLPED 2021 Best Paper Award","body":[{"value":"\u003Cp\u003EBrian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, and Arijit Raychowdhury\u0026nbsp;won the Best Paper Award at this year\u0026#39;s ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021). The symposium was held July 26-28 in a virtual format.\u003C\/p\u003E\r\n\r\n\u003Cp\u003ECrafton and Spetalnick are Ph.D. students in the Georgia Tech School of Electrical and Computer Engineering (ECE), where they are advised by Raychowdhury, who holds the Motorola Solutions Foundation Professorship. He also leads the Integrated Circuits and Systems Research Lab (ICSRL). Yoon was a postdoctoral researcher in ICSRL until December 2020, and he is now an assistant professor in the Department of Information and Communication Engineering at the Daegu Gyeongbuk Institute of Science and Technology in Daegu, South Korea.\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe title of the team\u0026rsquo;s paper is \u0026ldquo;Statistical Optimization of Compute In-Memory Performance Under Device Variation.\u0026rdquo; Compute in-memory using emerging non-volatile memory technologies is an exciting technique that promises to increase memory throughput and perform compute on the bitline of memory sub-arrays, thus accelerating machine learning workloads. However, this technique faces new challenges not before faced in traditional CMOS memory fabrics. The impact of the inherent spatial and temporal variations in memory cells is exacerbated when several are read on the same bitline. These variations result in significantly higher bit error-rates. \u0026nbsp;As a result, performance must be limited to mitigate the high error rate.\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThis work presents a novel technique to maximize the performance of compute in-memory while satisfying an error constraint. Error models are constructed based on measurements collected on a 40nm foundry array, and an optimization problem is formulated and solved using integer linear programming. Using this technique, an optimal tradeoff of performance and accuracy is met enabling significant speedup over prior work.\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThis research is funded by Air Force Office for Scientific Research through the CEREBRAL MURI program and by SRC through the JUMP programs.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EBrian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, and Arijit Raychowdhury\u0026nbsp;won the Best Paper Award at this year\u0026#39;s ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021).\u003C\/p\u003E\r\n","format":"limited_html"}],"field_summary_sentence":[{"value":"Brian Crafton, Samuel Spetalnick, Jong-Hyeok Yoon, and Arijit Raychowdhury\u00a0won the Best Paper Award at this year\u0027s ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021). "}],"uid":"27241","created_gmt":"2021-08-03 19:18:33","changed_gmt":"2021-08-03 19:33:36","author":"Jackie Nemeth","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2021-08-03T00:00:00-04:00","iso_date":"2021-08-03T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"hg_media":{"649233":{"id":"649233","type":"image","title":"ICSRL Team","body":null,"created":"1628019167","gmt_created":"2021-08-03 19:32:47","changed":"1628019167","gmt_changed":"2021-08-03 19:32:47","alt":"Photograph of ICSRL team - Pictured clockwise from upper left: Brian Crafton, Samuel Spetalnick, Arijit Raychowdury, and\u00a0Jong-Hyeok Yoon","file":{"fid":"246498","name":"ICSRL ISPLED paper award team.png","image_path":"\/sites\/default\/files\/images\/ICSRL%20ISPLED%20paper%20award%20team.png","image_full_path":"http:\/\/hg.gatech.edu\/\/sites\/default\/files\/images\/ICSRL%20ISPLED%20paper%20award%20team.png","mime":"image\/png","size":2970888,"path_740":"http:\/\/hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/ICSRL%20ISPLED%20paper%20award%20team.png?itok=1Nht0cN0"}}},"media_ids":["649233"],"related_links":[{"url":"https:\/\/icsrl.ece.gatech.edu\/","title":"Integrated Circuits and Systems Research Lab"},{"url":"http:\/\/www.ece.gatech.edu","title":"School of Electrical and Computer Engineering"},{"url":"http:\/\/www.gatech.edu","title":"Georgia Tech"},{"url":"https:\/\/www.islped.org\/2021\/","title":"ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021)"}],"groups":[{"id":"1255","name":"School of Electrical and Computer Engineering"}],"categories":[{"id":"134","name":"Student and Faculty"},{"id":"8862","name":"Student Research"},{"id":"135","name":"Research"},{"id":"145","name":"Engineering"},{"id":"149","name":"Nanotechnology and Nanoscience"},{"id":"150","name":"Physics and Physical Sciences"}],"keywords":[{"id":"181439","name":"Brian Crafton"},{"id":"186165","name":"Samuel Spetalnick"},{"id":"187805","name":"Jong-Hyeok Yoon"},{"id":"139771","name":"Arijit Raychowdhury"},{"id":"188397","name":"ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2021)"},{"id":"109","name":"Georgia Tech"},{"id":"166855","name":"School of Electrical and Computer Engineering"},{"id":"139781","name":"Integrated Circuits and Systems Research Lab"},{"id":"188398","name":"Daegu Gyeongbuk Institute of Science and Technology"},{"id":"188399","name":"Department of Information and Communication Engineering"},{"id":"188400","name":"statistical optimization"},{"id":"188401","name":"compute-in memory"},{"id":"188402","name":"emerging non-volatile memory technologies"},{"id":"188403","name":"memory sub-arrays"},{"id":"9167","name":"machine learning"},{"id":"186181","name":"CMOS memory fabrics"},{"id":"188404","name":"bit error-rates"},{"id":"188405","name":"Air Force Office for Scientific Research"},{"id":"166954","name":"SRC"}],"core_research_areas":[{"id":"39431","name":"Data Engineering and Science"},{"id":"39451","name":"Electronics and Nanotechnology"}],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003E\u003Ca href=\u0022mailto:jackie.nemeth@ece.gatech.edu\u0022\u003EJackie Nemeth\u003C\/a\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003ESchool of Electrical and Computer Engineering\u003C\/p\u003E\r\n","format":"limited_html"}],"email":["jackie.nemeth@ece.gatech.edu"],"slides":[],"orientation":[],"userdata":""}}}