Committee:

Dr. Rao Tummala, ECE, Chair , Advisor

Dr. Madhavan Swaminathan, ECE

Dr. Andrew Peterson, ECE

Dr. Azad Naeemi, ECE

Dr. Vanessa Smet, ME

Abstract: With the slowing down of Moore's law, HPC/AI systems today disaggregate large and expensive System-on-Chips (SoCs) and pursue on-package heterogeneous integration to meet the growing demands in compute performance and memory capacity. Hence, the bandwidth and power-efficiency (measured as energy-per-bit) of communication between these smaller chips becomes the limiting factor in scaling system performance. These two key metrics are primarily driven by I/O count, interconnect length, interconnect density, and the choice of dielectric materials. Today, the technology options for package-level integration are either 2D/3D and chip-first/chip-last, based on how the chips are assembled. While some 3D and chip-first technologies solve the interconnect length and I/O count challenges, they are still fundamentally limited in scaling the bandwidth and power-efficiency comprehensively. This work presents a novel, non-TSV, 3D packaging technology using Glass Panel Embedding (GPE) for next-generation HPC & AI systems with >1 Tbps/mm bandwidth at <0.1 pJ/bit power-efficiency. GPE simultaneously addresses I/O density and interconnect length while utilizing low-dk/df materials and low-loss polymer RDL technologies. The design of such a system is presented in this work along with a design-space exploration of key substrate parameters to assess the bandwidth and energy-per-bit potential of proposed structure. Materials and processes are also studied establishing a stable fabrication process flow to demonstrate such a 3D package in a panel-scalable, low-cost, and thermo-mechanically reliable fashion.