{"645279":{"#nid":"645279","#data":{"type":"event","title":"Ph.D. Dissertation Defense - Siddharth  Ravichandran","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle\u003C\/strong\u003E\u003Cem\u003E:\u0026nbsp; \u003C\/em\u003E\u003Cem\u003EDesign \u0026amp; Demonstration of 3D Glass Panel Embedded (GPE) Package for Superior Bandwidth and Power Efficiency\u003C\/em\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee:\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Rao Tummala, ECE, Chair , Advisor\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Madhavan Swaminathan, ECE\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Andrew Peterson, ECE\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Azad Naeemi, ECE\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Vanessa Smet, ME\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract:\u0026nbsp;\u003C\/strong\u003EWith the slowing down of Moore\u0026#39;s law, HPC\/AI systems today disaggregate large and expensive System-on-Chips (SoCs) and pursue on-package heterogeneous integration to meet the growing demands in compute performance and memory capacity. Hence, the bandwidth and power-efficiency (measured as energy-per-bit) of communication between these smaller chips becomes the limiting factor in scaling system performance. These two key metrics are primarily driven by I\/O count, interconnect length, interconnect density, and the choice of dielectric materials. Today, the technology options for package-level integration are either 2D\/3D and chip-first\/chip-last, based on how the chips are assembled. While some 3D and chip-first technologies solve the interconnect length and I\/O count challenges, they are still fundamentally limited in scaling the bandwidth and power-efficiency comprehensively. This work presents a novel, non-TSV, 3D packaging technology using Glass Panel Embedding (GPE) for next-generation HPC \u0026amp; AI systems with \u0026gt;1 Tbps\/mm bandwidth at \u0026lt;0.1 pJ\/bit power-efficiency. GPE simultaneously addresses I\/O density and interconnect length while utilizing low-dk\/df materials and low-loss polymer RDL technologies. The design of such a system is presented in this work along with a design-space exploration of key substrate parameters to assess the bandwidth and energy-per-bit potential of proposed structure. Materials and processes are also studied establishing a stable fabrication process flow to demonstrate such a 3D package in a panel-scalable, low-cost, and thermo-mechanically reliable fashion.\u0026nbsp;\u0026nbsp;\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Design \u0026 Demonstration of 3D Glass Panel Embedded (GPE) Package for Superior Bandwidth and Power Efficiency "}],"uid":"28475","created_gmt":"2021-03-12 14:08:14","changed_gmt":"2021-03-12 14:08:14","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2021-03-23T11:00:00-04:00","event_time_end":"2021-03-23T13:00:00-04:00","event_time_end_last":"2021-03-23T13:00:00-04:00","gmt_time_start":"2021-03-23 15:00:00","gmt_time_end":"2021-03-23 17:00:00","gmt_time_end_last":"2021-03-23 17:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434381","name":"ECE Ph.D. Dissertation Defenses"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78761","name":"Faculty\/Staff"},{"id":"78771","name":"Public"},{"id":"78751","name":"Undergraduate students"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}