{"641094":{"#nid":"641094","#data":{"type":"event","title":"PhD Defense by Bartlet DeProspo","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETHE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EGEORGIA INSTITUTE OF TECHNOLOGY\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EUnder the provisions of the regulations for the degree\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nDOCTOR OF PHILOSOPHY\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003Eon Thursday, November 19, 2020\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003E1:00 PM\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cbr \/\u003E\r\n\u003Cstrong\u003Evia\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EBluejeans Video Conferencing\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Ca href=\u0022https:\/\/bluejeans.com\/389380024\u0022\u003Ehttps:\/\/bluejeans.com\/389380024\u003C\/a\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003Ewill be held the\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EDISSERTATION\u0026nbsp;DEFENSE\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nfor\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EBartlet DeProspo\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003E\u0026quot;Modeling, Design and Demonstration of 1 \u0026micro;m Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications\u0026quot;\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee Members:\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EProf. Rao Tummala, Advisor, ECE\/MSE\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EProf. Madhavan Swaminathan, ECE\/MSE\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EProf. Mark Losego, MSE\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EProf. Paul Kohl, CHBE\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EProf. Azad Naeemi, ECE\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ELeonel Arana, PhD, Intel Corporation\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract:\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThere has been tremendous research in driving the technologies for integrated circuit (IC) device scaling since the mid-1900s. The primary driver\u0026nbsp;of\u0026nbsp;device scaling, Moore\u0026rsquo;s Law, states that the number\u0026nbsp;of\u0026nbsp;transistors in an integrated circuit (IC) doubles every two years.\u0026nbsp;As IC device scaling is slowing down in recent times, new solutions are being undertaken to improve performance\u0026nbsp;of\u0026nbsp;the entire system. Since 2010, heterogeneous integration\u0026nbsp;of\u0026nbsp;multiple ICs on to a package substrate has become one\u0026nbsp;of\u0026nbsp;the most popular solutions to improve system performance\u0026nbsp;and\u0026nbsp;miniaturization to support high performance computing (HPC) applications.\u0026nbsp;Thus, package substrate technology has been a huge enabler to system scaling in terms\u0026nbsp;of\u0026nbsp;overall miniaturization, high bandwidth performance\u0026nbsp;and\u0026nbsp;high density\u0026nbsp;of\u0026nbsp;interconnections between heterogeneous dies to enable more operations per second.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe research in this thesis work focuses on the redistribution layer (RDL) technology for high density interconnections between two ICs. The state\u0026nbsp;of\u0026nbsp;the art HPC applications utilize silicon back-end-of-line processing for high bandwidth capable\u0026nbsp;of\u0026nbsp;scaling RDL critical dimensions to submicron. However, they face two challenges in terms\u0026nbsp;of: (A) High RC delay RDL wiring connections slowing down the system performance, (B) Limited aspect ratio scaling due to mechanically unstable dielectrics. Glass interposer is a promising alternative solution to this problem. The polymer dielectric based RDL technology for panel platforms is still limited to 5-6 micron features\u0026nbsp;and\u0026nbsp;the research focuses on scaling to 1 micron RDL in three target areas: (A) Modeling\u0026nbsp;and\u0026nbsp;Design for high density\u0026nbsp;and\u0026nbsp;low resistance 1 micron RDL, (B) Fundamental development\u0026nbsp;and\u0026nbsp;performance evaluation\u0026nbsp;of\u0026nbsp;materials\u0026nbsp;for the fabrication\u0026nbsp;of\u0026nbsp;1 micron RDL on panel platforms\u0026nbsp;and, (C) Innovative process solutions for scaling glass panel RDL to 1 micron line, space\u0026nbsp;and\u0026nbsp;via.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe first target area addresses the modeling\u0026nbsp;and\u0026nbsp;design for high density\u0026nbsp;and\u0026nbsp;high performance 1 micron RDL to understand impact\u0026nbsp;of\u0026nbsp;aspect ratio\u0026nbsp;and\u0026nbsp;design rules for maximization\u0026nbsp;of\u0026nbsp;performance. The second area focuses on developing\u0026nbsp;and\u0026nbsp;evaluation\u0026nbsp;of\u0026nbsp;fundamental differences between\u0026nbsp;materials\u0026nbsp;used in BEOL processing for achieving sub-micron resolutions\u0026nbsp;and\u0026nbsp;those utilized in panel scale process. The goal\u0026nbsp;of\u0026nbsp;this material evaluation\u0026nbsp;and\u0026nbsp;development is to scale the lithographic performance as well as support high aspect ratio traces. The third\u0026nbsp;and\u0026nbsp;final area will focus on the study\u0026nbsp;of\u0026nbsp;substrate impacts on the ability to fabricate high performance 1 micron RDL on panel format technologies. This third area will also focus on innovative processing solutions for scaling seed layer etch as well as via resolution\u0026nbsp;and\u0026nbsp;alignment.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"\u0022Modeling, Design and Demonstration of 1 \u00b5m Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications"}],"uid":"27707","created_gmt":"2020-11-06 20:43:45","changed_gmt":"2020-11-06 20:43:45","author":"Tatianna Richardson","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2020-11-19T13:00:00-05:00","event_time_end":"2020-11-19T15:00:00-05:00","event_time_end_last":"2020-11-19T15:00:00-05:00","gmt_time_start":"2020-11-19 18:00:00","gmt_time_end":"2020-11-19 20:00:00","gmt_time_end_last":"2020-11-19 20:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"221981","name":"Graduate Studies"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78761","name":"Faculty\/Staff"},{"id":"78771","name":"Public"},{"id":"174045","name":"Graduate students"},{"id":"78751","name":"Undergraduate students"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}