The war in Iran has dominated headlines with reports of airstrikes and escalating military activity. But beyond the immediate devastation, the conflict has also illuminated a quieter and rapidly growing danger: the vulnerability of ships, and the people who operate them, to disruption of their navigation systems.

Modern shipping depends heavily on GPS satellite navigation. When those signals are disrupted or manipulated, ships can suddenly appear to their navigators and to other ships to be somewhere they are not. In some cases, vessels have been shown jumping across maps, drifting miles inland or appearing to circle in impossible patterns. The risk is even higher in war zones, where ships could be misdirected into harm’s way.

As a cybersecurity researcher studying critical infrastructure and maritime systems, I investigate how digital threats affect ships and the people who operate them.

To understand the threat from GPS disruptions, it helps to first understand how GPS works. GPS systems determine location using signals from satellites orbiting Earth. A receiver calculates its position by measuring how long those signals take to arrive. Because those signals are extremely weak by the time they reach Earth, they are relatively easy to disrupt.

GPS Jamming and Spoofing

In GPS jamming, an attacker blocks the real satellite signals by overwhelming them with electromagnetic noise so receivers cannot detect them. When this happens, navigation systems lose their position. On a phone, it might look like the map freezing or jumping erratically.

GPS spoofing is more sophisticated. Instead of blocking signals, an attacker transmits fake satellite signals designed to mimic the real ones. The receiver accepts these signals and gives a false location. Imagine driving north while your navigation system suddenly insists you are traveling south. The receiver is not malfunctioning; it has simply been tricked.

For mariners at sea, spoofing can have serious consequences. In the open ocean, there are few landmarks to verify a ship’s position if GPS behaves strangely. Nearshore, the margin for error disappears: Water depths change quickly and hazards are everywhere, especially in narrow routes like the Strait of Hormuz near Iran, where reports indicate that GPS spoofing has been happening since the outbreak of the war. Because ships are large and slow to maneuver, even small navigation errors can lead to groundings or collisions.

Red Sea Grounding

One example came in May 2025. While transiting the Red Sea, the container ship MSC Antonia began showing positions far from its true location. To navigators onboard, this looked like they had jumped hundreds of miles south on the map and started moving in a new direction. This caused the crew to become disoriented, and the ship eventually ran aground. The grounding caused millions of dollars in damage and required a salvage operation that lasted over five weeks.

Incidents like the MSC Antonia are not isolated. Vessel-tracking data has revealed clusters of ships suddenly appearing in impossible locations, sometimes far inland or moving in perfect circles. These anomalies are increasingly linked to GPS spoofing in regions experiencing geopolitical conflict.

But GPS interference is only one type of cyber threat facing ships. Industry reports have documented ransomware attacks on shipping companies, supply chain compromises and increasing concern about the security of onboard control systems, including engines, propulsion and navigation equipment. As ships become more connected through satellite internet systems and remote monitoring tools, the number of potential entry points for cyberattacks is growing.

Military vessels often address these risks through stricter network segregation and regular training exercises such as “mission control” drills, which simulate operating with compromised communications or navigation systems. Some cybersecurity experts argue that similar practices could help commercial shipping improve its resilience, although smaller crews and limited resources make adopting military-style procedures more difficult.

Mariners’ Experiences

Much of the public discussion around maritime cybersecurity focuses on technical vulnerabilities in ship systems. But an equally important piece of the puzzle is the people who must interpret and respond to these technologies when something goes wrong.

In recent research, my colleagues and I interviewed professional mariners about their experiences with cyber incidents and their preparedness to respond to them. The interviews included navigation officers, engineers and other crew members responsible for ship systems. What emerged was a consistent picture: Cyber threats are increasingly occurring at sea, but crews are not well prepared to deal with them.

Many mariners told us that their cybersecurity training focused almost entirely on email phishing and USB drives. That kind of training may make sense in an office, but it does little to prepare crews for cyber incidents on a ship, where navigation and control systems can be the primary targets. As a result, many mariners lack clear guidance on how cyberattacks might affect the equipment they rely on every day.

This becomes a problem when ship systems begin behaving strangely. Mariners described GPS showing incorrect positions or temporarily losing signal. It can be difficult to tell whether these incidents are equipment failures or signs of cyber interference.

Even when mariners suspect something may be wrong, many ships lack clear procedures for responding to cyber incidents. Participants frequently described situations where they would have to improvise if navigation or other digital systems behaved unexpectedly. Unlike equipment failures, which have established checklists and procedures, cyber incidents often fall into a gray area where responsibility and response plans are unclear.

Another challenge is the gradual disappearance of traditional navigation practices. For centuries, mariners relied on paper charts and celestial navigation to determine their position. Today, most commercial vessels rely almost entirely on electronic systems.

Many mariners noted that paper charts are not available onboard, and celestial navigation is rarely practiced. If GPS or electronic navigation systems fail, crews have limited ways to independently verify their position. One mariner bluntly described the risk to us: “If you don’t have charts and you’re being spoofed, you’re a little screwed.”

Increasing Connectivity, Increasing Risk

At the same time, ships are becoming more connected. Modern vessels increasingly rely on satellite internet systems like Starlink and remote monitoring tools to manage operations and communicate with shore.

While these technologies improve efficiency, they also expand the vulnerability of ship systems. Connectivity that allows crews to send emails or access the internet can also provide pathways for cyber threats to reach onboard systems.

As GPS spoofing becomes more common in regions experiencing geopolitical conflict, the challenges mariners described in our research are becoming harder to ignore. The oceans may seem vast and empty, but the digital signals that guide modern ships travel through crowded and contested space.

When those signals are manipulated, the consequences do not stay confined to military systems. They reach the commercial vessels that carry most of the world’s goods and the crews responsible for navigating them safely.

This article is republished from The Conversation under a Creative Commons license. Read the original article.

From drones delivering medical supplies to digital assistants performing everyday tasks, AI-powered systems are becoming increasingly embedded in everyday life. The creators of these innovations promise transformative benefits. For some people, mainstream applications such as ChatGPT and Claude can seem like magic. But these systems are not magical, nor are they foolproof – they can and do regularly fail to work as intended.

AI systems can malfunction due to technical design flaws or biased training data. They can also suffer from vulnerabilities in their code, which can be exploited by malicious hackers. Isolating the cause of an AI failure is imperative for fixing the system.

But AI systems are typically opaque, even to their creators. The challenge is how to investigate AI systems after they fail or fall victim to attack. There are techniques for inspecting AI systems, but they require access to the AI system’s internal data. This access is not guaranteed, especially to forensic investigators called in to determine the cause of a proprietary AI system failure, making investigation impossible.

We are computer scientists who study digital forensics. Our team at the Georgia Institute of Technology has built a system, AI Psychiatry, or AIP, that can recreate the scenario in which an AI failed in order to determine what went wrong. The system addresses the challenges of AI forensics by recovering and “reanimating” a suspect AI model so it can be systematically tested.

Uncertainty of AI

Imagine a self-driving car veers off the road for no easily discernible reason and then crashes. Logs and sensor data might suggest that a faulty camera caused the AI to misinterpret a road sign as a command to swerve. After a mission-critical failure such as an autonomous vehicle crash, investigators need to determine exactly what caused the error.

Was the crash triggered by a malicious attack on the AI? In this hypothetical case, the camera’s faultiness could be the result of a security vulnerability or bug in its software that was exploited by a hacker. If investigators find such a vulnerability, they have to determine whether that caused the crash. But making that determination is no small feat.

Although there are forensic methods for recovering some evidence from failures of drones, autonomous vehicles and other so-called cyber-physical systems, none can capture the clues required to fully investigate the AI in that system. Advanced AIs can even update their decision-making – and consequently the clues – continuously, making it impossible to investigate the most up-to-date models with existing methods.

Pathology for AI

AI Psychiatry applies a series of forensic algorithms to isolate the data behind the AI system’s decision-making. These pieces are then reassembled into a functional model that performs identically to the original model. Investigators can “reanimate” the AI in a controlled environment and test it with malicious inputs to see whether it exhibits harmful or hidden behaviors.

AI Psychiatry takes in as input a memory image, a snapshot of the bits and bytes loaded when the AI was operational. The memory image at the time of the crash in the autonomous vehicle scenario holds crucial clues about the internal state and decision-making processes of the AI controlling the vehicle. With AI Psychiatry, investigators can now lift the exact AI model from memory, dissect its bits and bytes, and load the model into a secure environment for testing.

Our team tested AI Psychiatry on 30 AI models, 24 of which were intentionally “backdoored” to produce incorrect outcomes under specific triggers. The system was successfully able to recover, rehost and test every model, including models commonly used in real-world scenarios such as street sign recognition in autonomous vehicles.

Thus far, our tests suggest that AI Psychiatry can effectively solve the digital mystery behind a failure such as an autonomous car crash that previously would have left more questions than answers. And if it does not find a vulnerability in the car’s AI system, AI Psychiatry allows investigators to rule out the AI and look for other causes such as a faulty camera.

Not Just for Autonomous Vehicles

AI Psychiatry’s main algorithm is generic: It focuses on the universal components that all AI models must have to make decisions. This makes our approach readily extendable to any AI models that use popular AI development frameworks. Anyone working to investigate a possible AI failure can use our system to assess a model without prior knowledge of its exact architecture.

Whether the AI is a bot that makes product recommendations or a system that guides autonomous drone fleets, AI Psychiatry can recover and rehost the AI for analysis. AI Psychiatry is entirely open source for any investigator to use.

AI Psychiatry can also serve as a valuable tool for conducting audits on AI systems before problems arise. With government agencies from law enforcement to child protective services integrating AI systems into their workflows, AI audits are becoming an increasingly common oversight requirement at the state level. With a tool like AI Psychiatry in hand, auditors can apply a consistent forensic methodology across diverse AI platforms and deployments.

In the long run, this will pay meaningful dividends both for the creators of AI systems and everyone affected by the tasks they perform.

This article is republished from The Conversation under a Creative Commons license. Read the original article.

The human body constantly generates a variety of signals that can be measured from outside the body with wearable devices. These bio-signals – ranging from heart rate to sleep state and blood oxygen levels – can indicate whether someone is having mood swings or can be used to diagnose a variety of body or brain disorders.

It can be relatively cheap to gather a lot of bio-signal data. Researchers can organize a study and ask participants to use a wearable device akin to a smartwatch for a few days. However, to teach a machine learning algorithm to find a relationship between a specific bio-signal and a health disorder, you first need to teach the algorithm to recognize that disorder. That’s where computer engineers like myself come in.

Many commercial smartwatches, such as ones by Apple, AliveCor, Google and Samsung, currently support atrial fibrillation detection. Atrial fibrillation is a common type of irregular heart rhythm, and leaving it untreated can lead to a stroke. One way to automatically detect atrial fibrillation is to train a machine learning algorithm to recognize what atrial fibrillation looks like in the data.

This machine learning approach requires large bio-signal datasets in which instances of atrial fibrillation are labeled. The algorithm can use the labeled instances to learn to recognize a relationship between the bio-signal and atrial fibrillation.

The labeling process can be quite expensive because it requires experts, such as cardiologists, to go through millions of data points and label each instance of atrial fibrillation. The same problem extends to many other bio-signals and disorders.

To resolve this issue, researchers have been developing new ways to train machine learning algorithms with fewer labels. By first training a machine learning model to fill in the blanks of large-scale unlabeled bio-signal data, the machine learning model is primed to learn the relationship between a bio-signal and a disorder with fewer labels. This is called pretraining. Pretraining even helps a machine learning model learn a relationship between a bio-signal and a disorder when it is pretrained on a completely unrelated bio-signal.

Challenges of Working With Bio-Signals

Finding relationships between bio-signals and disorders can be difficult because of noise, or irrelevant data, differences between people’s bio-signals, and because the relationship between a bio-signal and disorder may not be clear.

First, bio-signals contain a lot of noise. For example, when you’re wearing a smartwatch while running, the watch will move around. This causes the sensor for the bio-signal to record at different locations during the run. Since the locations vary across the run, swings in the bio-signal value may now be due to variations in the recording location instead of due to physiological processes.

Second, everyone’s bio-signals are unique. The location of veins, for example, often differ between people. This means that even if smartwatches are worn at exactly the same place on everyone’s wrists, the bio-signal related to those veins is recorded differently from one person to the next. The same underlying signal, such as someone’s heart rate, will lead to different bio-signal values.

The underlying signal itself can also be unique for people or groups of people. The resting heart rate of an average person is around 60-80 beats per minute, but athletes can have resting heart rates as low as 30-40 beats per minute.

Lastly, the relationship between a bio-signal and a disorder is often complex. This means that the disorder is not immediately obvious from looking at the bio-signal.

Machine learning algorithms allow researchers to learn from data and account for the complexity, noise and variability of people. By using large bio-signal datasets, machine learning algorithms are able to find clear relationships that apply to everyone.

Learning to Fill in the Blanks

Researchers can use unlabeled bio-signal data as a warmup for the machine learning algorithm. This warmup, or pre-training, primes the machine learning algorithm to find a relationship between the bio-signal and a disorder. This is a bit like walking around a park to get the lay of the land before working out a route to go running.

There are many ways to pretrain a machine learning algorithm. In my research with Dolby Laboratories researcher Lie Lu and previous research, the machine learning algorithm is taught to fill in the blanks.

To do this, we take a bio-signal and artificially create gaps of a certain length – for example, one second. We then teach the machine learning algorithm to fill in the missing piece of bio-signal. This is possible because the machine learning algorithm sees what the bio-signal looks like before and after the gap.

If the heart rate of a person is around 60 beats per minute before the gap, there will likely be a heartbeat in the one-second gap. In this case, we’re training the machine learning algorithm to predict when that heartbeat will occur.

Once we have trained the machine learning algorithm to do this, it will have found a relationship between someone’s heart rate and when the next beat should occur. We can now train the machine learning algorithm with this relationship between a normal heart rate and bio-signal already learned. This makes it easier for the algorithm to learn the relationship between heart rate and atrial fibrillation. Since atrial fibrillation is characterized by fast and irregular heartbeats, and the algorithm is now good at predicting when a heartbeat will happen, it can quickly learn to detect these irregularities.

The idea of filling in the blanks can be generalized to other bio-signals as well. Previous research has shown, and our work reconfirmed, that pretraining a model on one bio-signal without any labels allows it to learn clinically useful relationships from other bio-signals with few labels. This shortcut means that researchers can pretrain on bio-signals that are easy to gather and use the machine learning model on ones that are hard to gather and label.

Faster Disorder Detection Development

By improving pretraining, researchers can make machine learning algorithms better and more efficient at detecting diseases and disorders. Pretraining improvements reduce cost and time spent by experts labeling.

A recent example of machine learning algorithms used for early detection is Google’s Loss of Pulse smartwatch feature. The emerging field of bio-signal pretraining can help enable faster development of similar features using a wider range of bio-signals and for a wider range of disorders.

With increasing types of bio-signals and more data, researchers may be able to discover relationships that dramatically improve early detection of disease and disorders. The earlier many diseases and disorders are found, the better a treatment plan works for patients.

This article is republished from The Conversation under a Creative Commons license. Read the original article.

Hao started at ECE in 2020 as a postdoctoral fellow, then becoming an assistant professor in 2021. She is the director for the Software/Hardware Co-Design for Intelligence and Efficiency (Sharc) Lab, while also being part of the VLSI Systems and Digital Design Technical Interest Group.

“I’m deeply honored to receive the ON Semiconductor Junior Professorship," Hao said. "It means a lot to have my work recognized in this way, especially as agile chip design becomes such a key part of our AI-driven future. I’m excited and grateful for the chance to keep building, learning, and mentoring—this support will help me do even more meaningful research and teaching.”

Hao’s research focuses on agile software/hardware co-design, especially in the joint area of efficient hardware design and machine learning algorithms. She is also passionate about reconfigurable and high-efficiency computing and building useful electronic design automation tools.

She’s received a number of awards and distinctions during her time at ECE, including the NSF CAREER Award and the Intel Rising Star Faculty Award. Additionally, Hao previously held the Sutterfield Family Early Career Professorship for the last two years.

Their proposal, “Network-on-X (NoX): Hierarchical Interconnect Modeling & DSE for 2.5D/3D Chiplet Architectures,” was one of only 17 selected from a highly competitive pool of 266 submissions across North America, and the only winning team from Georgia Tech.

Kim and Baig’s project, NoX, addresses a critical gap in modern chiplet-based system design. As the industry shifts toward 2.5D and 3D integration, existing tools fail to account for the intricate interactions between architecture and packaging. NoX proposes a cross-layer simulation framework that models hierarchical communication while incorporating real-world packaging constraints—enabling more accurate and scalable design space exploration for AI and high-performance computing (HPC) systems.

The QIF program invests in Ph.D. students across a broad range of technical research areas, empowering them to take steps toward achieving their research goals. The fellowship will provide Baig and Kim with one year of support to pursue their research, as well as offer mentorship from Qualcomm engineers.

Kim is advised by professor Cong (Callie) Hao in the Sharc Lab. Her research focuses on field programmable gate arrays design and architecture-packaging co-design, with an emphasis on developing technology-aware simulators for emerging chiplet-based systems. She interned at IBM Research in 2024 and will be a visiting scholar at ETH Zurich this summer. Her recent work was nominated for Best Paper at 2025 IEEE International Symposium on Field-Programmable Custom Computing Machines.

Baig is advised by professor Muhannad Bakir at the Integrated 3D Systems Lab. He received his B.A. in nanotechnology engineering from the University of Waterloo in Canada, after which he worked as an optoelectronics design engineer and patented novel techniques for large-area printing of microdevices. His current research focuses on chiplet bonding using nanoscale interconnects. He is on a summer internship at Analog Devices as an advanced packaging intern.

Georgia Tech researchers have been meeting with the choreographer, Troy Schumacher, and the ballet company for the last year and a half to shape the concept, which explores ideas at the forefront of mechanical interventions into the human body and mind.

“I think the arts can be a really powerful way to bring people from all backgrounds into a conversation about science and technology,” said Chris Rozell, a professor in the School of Electrical and Computer Engineering who has worked on the project since its genesis. “My goal is to facilitate that conversation by helping to translate between the scientists doing amazing work and the artists who are approaching these ideas from the perspective of making something beautiful.”  

Georgia Tech Arts and TMBT have dubbed the project the “Grand Neuroethics Challenge.”

“A lot of the concepts, technologies, research, and ethics we've been discussing in this work are extremely complicated, but what's come through for me is that a lot of their work is going to have profound implications for the future of humanity,” said Schumacher. “So, for this ballet, I've decided to focus on the emotional relationship to brain-machine interfaces, while touching on what I've learned so far. I've spent most of my career collaborating with artists with little to no relationship to dance, but nothing quite as complex and fascinating as this.”

Aaron Shackelford, director of Georgia Tech Arts, said the project is a worthwhile endeavor because it offers a case study as to the importance of collaboration between artists and researchers, while demonstrating the importance of the arts in the mission and strategic plan of Georgia Tech.

“We recognize that the arts are critical to championing innovation and creativity at Georgia Tech,” said Shackelford. “Our mission is to develop leaders who advance technology and improve the human condition. The arts — and artists — provide a vital avenue for pursuing this work. This project illuminates the impact of artists and researchers coming together to mutually inspire and learn from each other, while inviting audiences to participate in the discussions about their discoveries.”

“As a director coming from an arts/dance background and facilitator to this project, I have become fascinated with the work of the scientists during the conceiving/creation process and how this gets interwoven into the choreography and dancers’ bodies,” said John Welker, TMBT’s artistic director. “In any collaboration, there are surprises that are part of my joy for discovery, but this particular process has made me so much more aware and appreciative of the intimate connection between our minds' intention and how that is carried out through the movement of our bodies.”

This Friday will be more than a dance performance. It will also include talks from the researchers involved in the project and opportunities for audience to ask questions. Rozell will discuss his work on AI and its applications in treating depression. Chethan Pandarinath, assistant professor in the Wallace H. Coulter Department of Biomedical Engineering at Emory University and Georgia Tech, will talk about his AI research and how the brain controls movement. They’ll be joined by Karen Rommelfanger, director of Emory’s Neuroethics Program.

Rommelfanger knows the field of neuroscience can introduce complex words and concepts. When mixed with dance, however, she sees the project as a powerful opportunity for audiences to engage with multiple modalities of sensation and comprehension.

“I believe neuroscience brings great hope and promise for humanity. But my fear is that the promise of the field will be undermined by a deterioration of trust related to a real and hyped threats of unconsidered ways neuroscience might interface with individuals and society,” said Rommelfanger.” My hope is that this project will invite audiences, including myself, to challenge and surface our unspoken values and assumptions about the brain and technologies that interface with it.”

Friday’s event starts at 8pm at the Ferst Center for the Arts. Tickets are just $10. The full work, which is made possible in part through a grant from the Charles Loridans Foundation, will premiere on campus next fall.

“I’m excited to see how something as abstract as the concepts in neuroscience, neurotechnology, and neuroethics can be translated into dance,” Rozell said. “As a researcher, we can get really caught up in the technical details. I can’t wait to see how those details turn into an overall impression that is both beautiful and gives us a new way to think about what we do.”

Naeemi, who is an ECE graduate and joined the faculty in 2008, was selected to the five-year appointment for his exceptional record of scholarship and service to the Institute. Criteria for the designation of Dean's Professor include outstanding scholarship, dedication to education, and excellence in service at Institutional and national/international levels.

His research crosses the boundaries of materials, devices, circuits, and systems investigating integrated circuits based on conventional and emerging nanoelectronic and spintronic devices and interconnects.

Currently, the main focus of Naeemi’s research is to develop a comprehensive end-to-end modeling and optimization framework for emerging memory and logic devices starting with fundamental physics to devices, and then to circuits and applications.

He conducts this research out of the Nanoelectronics Research Lab, where is the director. Ferroelectric and magnetic devices are of particular interest for his group. They are also working on an academic process design kit (PDK) for one of the most advanced CMOS technology nodes (3nm) to enable Design-Technology Co-Optimization (DTCO).

Naeemi leads a six-university effort supported by the National Science Foundation to develop and evaluate interactive visualizations and simulation tools that help students gain better conceptual understanding of semiconductor physics and devices. The tools from this effort are being used by thousands of students around the world.

He’s received a number of prestigious awards, including the IEEE Electron Devices Society (EDS) Paul Rappaport Award for the best paper in the 2007 IEEE Transactions on Electron Devices journal, an NSF CAREER Award, an SRC Inventor Recognition Award, and several best paper awards at international conferences. He is also the first recipient of the IEEE Solid-State Circuits Society James D. Meindl Innovators Award. Judged by the direct vote of the ECE senior class, he was awarded W. Marshall Leach/Eta Kappa Nu Outstanding Senior Teacher Award in 2023.

In addition to his educational and research responsibilities, he also serves as the editor-in-chief of the IEEE Journal on Exploratory Computational Devices and Circuits and is the associate director for computation for the NSF-supported National Nanotechnology Coordinated Infrastructure.

Naeemi has been at Georgia Tech since 1999, first a graduate student, getting his M.S. and Ph.D. degrees in electrical and computer engineering from the Institute in 2001 and 2003, respectively.

He then worked as a research engineer in the Microelectronics Research Center at Georgia Tech from 2004 to 2008, before joining the ECE faculty.

Prior to Georgia Tech, he received his B.S. degree in electrical engineering from Sharif University, Tehran, Iran in 1994. After his undergraduate studies, he stayed in Tehran, where he worked as a design engineer with Partban and Afratab Companies.

After three impactful semesters of service, Richard Asiamah is passing the torch to a new team that will guide the GSO into the future.

“I am proud of the successes and impact my team and I have made over the past couple of semesters,” Asiamah said, reflecting on his tenure. “We continuously sought to enrich the student experience through the myriad of activities organized to build capacity, encourage socialization, and overall enhance graduate life at Georgia Tech.”

For the Fall 2025 semester, Himanshi Gupta, an ECE graduate student, will serve as president of the GSO. Beginning in Spring 2026, leadership will transition to Faaiq Waqar, a third-year Ph.D. student.

The organization is confident in the next generation of leadership and excited to see where they take the organization.

Both Gupta and Waqar have played active roles in the GSO over the past several semesters, contributing significantly to the planning and execution of many events.  

“At ECE GSO, we strive to make the graduate experience at Georgia Tech more engaging and collaborative by bringing together peers, faculty, and advisors in meaningful ways,” Gupta said. “From professional development to social gatherings, we host a wide range of events that foster connection and growth. I’m excited to work with an incredible team this year to further enhance the ECE community experience.”

“I’m excited to be leading an excellent team,” Faaiq said. “If you’re a student with ideas for improving the ECE graduate experience—or if you’d just like to get involved—feel free to reach out. I’d love to connect!”

Anyone with questions or wanting to get involved can reach out to the GSO or any of the new officers directly.

Contact Information: 
ECE GSO: gso@gatech.edu 
Himanshi Gupta: himanshigupta@gatech.edu 
Faaiq Waqar: faaiq.waqar@gatech.edu 

The prestigious three-year award is given to South Korea’s top graduate students in the field of medical bioscience.

Yun’s research interests lie at the intersection of biophotonics, nanophotonics, and image processing. Her work involves optical experiments, image processing, nanofabrication, and optimization at both the imaging system and device structure levels, all toward the development of advanced imaging technologies for biomedical applications.

Currently, she’s working  to enhance spatio-temporal resolution of optical microscopy by integrating high-speed camera systems, such as SPAD arrays, with advanced image processing algorithms to achieve high-SNR imaging with ultra-high spatial and temporal resolution for biomedical applications.

She’s also working on the development of photonic devices for advanced imaging. The goal is to design and optimize nanophotonic structures for applications like single-shot hyperspectral imaging to enhance optical functionalities.

Yun received her B.S. and M.S. in mechanical engineering from Pohang University of Science and Technology (POSTECH) in South Korea. During her master’s degree, she published multiple papers on the design strategies of metasurfaces and other nanophotonic structures for applications including wide field-of-view depth imaging and radiative cooling.

As she pursues her Ph.D. in ECE, she aims to apply her background in light-matter interactions and design optimization to develop advanced bio-imaging systems that exploit higher degrees of freedom of light—such as polarization, phase, and spectral properties—and leverage complex photonic behaviors to push the frontiers of biomedical imaging.

The Asan Foundation is a South Korean social welfare foundation that supports the betterment of human society through research funding and a number of other activities.

The full-day event was entirely student-organized and provided a unique opportunity for the DCL community to share research, foster interdisciplinary collaboration, and engage in discussions at the frontier of control theory, robotics, and decision-making. The symposium was funded by the Demetrius T. Paris Junior Professorship, held by School of Electrical and Computer Engineering (ECE) associate professor Sam Coogan.

"We have a long tradition in ECE of hosting the DCL student symposium annually,” Coogan said. “It's a great opportunity for students, postdocs, and faculty from across campus to come together for a day of sharing research and finding new connections. And it's completely student-organized and student-led. The student organizing committee gains valuable experience planning a meeting like this—a skill that proves useful whether they pursue careers in academia or industry."

In the morning, students participated in a series of rapid two-minute talks consisting of concise snapshots of their research, followed by a poster session. This format encouraged spontaneous discussion and collaboration among attendees. In the afternoon, students had the opportunity to present longer, 15 minute, spotlight talks of their research.

“The symposium is an excellent opportunity for student researchers to practice presenting their work in a low-stakes academic context,” said Akash Harapanahalli, a Ph.D. student working with Coogan, and the chair of the organizing committee. “My favorite part of organizing the event was being able to bring together participants from all over campus—including the Schools of Electrical and Computer Engineering, Mechanical Engineering (ME), Aerospace Engineering (AE), Industrial and Systems Engineering (ISyE), and Chemical and Biomolecular Engineering (ChBE)—who each had unique perspectives to offer”.

The symposium also featured four keynote presentations from Georgia Tech faculty: ISyE associate professor Siva Theja Maguluri, AE associate professor Yongxin Chen, ME assistant professor Shreyas Kousik, and AE assistant professor Lu Gan, who provided interesting perspectives on the varying theoretical and applied aspects of decision making, control, optimization, and robotics.

There was also a thought-provoking panel entitled “The Future of Decision-Making and Control,” where Kousik, AE assistant professors Glen Chou and Sarah Li, along with ECE research engineer Chih-Yuan (Frank) Chiu answered several student questions ranging from the importance of safety in the modern era, to how to survive as an academic.

The DCL Symposium continues to serve as a vibrant platform for students to showcase their work, receive feedback from peers and faculty, and connect across research labs. The organizing committee extends their thanks to all speakers, attendees, and participants who helped make the 2025 event a success.

Anyone wanting to participate in future years, or be added to the DCL mailing list, please email Akash Harapanahalli at aharapan@gatech.edu.

His paper, “Heterogeneous Integration Enabled by 3D Stitch-Chips," recently won the Best Paper Award in the Advanced Packaging Technologies from the IEEE Transactions on Components, Packaging and Manufacturing Technology, a premier package design publication.

Traditional chip interconnect methods like wire-bonding or flip-chip mounting either struggle with signal integrity at high frequencies or require complex fabrication steps.

The paper introduces a new interconnect technology called the 3D Stitch-Chip (3DSC), which offers a novel solution to the limitations of traditional interconnection methods such as wire bonding, die-embedding, and flip-chip bonding. Existing methods can be bulky, hard to manufacture, or cause issues with signal quality, especially when dealing with fast, high-frequency signals used in modern electronics.

3DSC avoids these problems by using a special structure that includes vertical channels and lateral connectors to link chips together. This allows the chips to be mounted face-up, without digging cavities, and helps keep signals clear even at very high speeds. This new method was successfully demonstrated for Ka-band frequencies (26-40 gigahertz), which are used in cutting-edge wireless and radar systems. Its modular design makes it especially useful for building complex systems that combine many different chips in a compact space.

He, along with his co-authors— Ph.D. students Zhonghao Zhang and Geyu Yan, and Georgia Tech Research Institute senior research engineer Paul K. Jo—conducted the research under the guidance of professor Muhannad S. Bakir, as part of the Integrated 3D Systems Group.

The work contributes to the group’s broader mission to rethink packaging architectures for heterogeneous integration, enabling future radio frequency systems to be smaller, faster, and more efficient.

Oh, Zhang, Jo, and Bakir will accept the award during the 75th Electronic Components and Technology Conference.

Fourth-year electrical engineering major Susannah Gordon and third-year electrical engineering major Radhika Sharma became the latest ECE students to win the selective award, joining Denitsa Dimitrova who won it last year.

The PES Scholarship Plus Initiative provides scholarships and real-world experience to undergraduates majoring in electrical engineering, who are high achievers with strong GPAs, distinctive extracurricular involvement, and are committed to pursuing careers in power and energy engineering.

Gordon and Sharma were two of just 84 winners from around North America.

On top of the PES Scholarship, Gordon won the John W. Estey Outstanding Scholar Award, which goes to the top PES student in each of the organization’s seven regions. She was chosen as the winner for Region 3.

Gordon’s academic path follows the Electric Energy Systems and Robotics curriculum threads. She has been interested in renewable energy and power engineering since her first year when she joined the Gaming for Electric Power Grids Vertically Integrated Project.

She’s conducted research with ECE associate professor Daniel Molzahn, focusing on generating a synthetic distribution system model for the State of Georgia based on public available information.

On campus, she is involved in ECE Ambassadors, Ramblin’ Reck Club, and Tau Beta Pi.

Upon graduating in May, she will join Kimley-Horn full time as an electrical analyst and hopes to pursue of a master’s degree in electrical engineering part-time at Georgia Tech.

Sharma has been involved in a number of campus organizations, including the Energy Club at Georgia Tech since her first semester at Georgia Tech, where she plans Energy Chats and networking events, along with helping to organize the Southeastern Energy Conference every year.

She’s also on the officer board of Women in ECE (WECE) and is a peer instructor at the Interdisciplinary Design Commons (also known as the Hive Makerspace).

Outside of Georgia Tech she’s completed two internships in power systems. One in power delivery at Florida Power & Light and another in substation design at Burns & McDonnell.

Her main research interest is in scaling the electric power grid. She also conducts research in power reliability with renewable energy sources.

Sharma plans to use the scholarship to finish the fourth year of her degree and use the PES resources that come with it to learn more about the different fields of power systems.

Applications for the 2025 cycle PES Scholarship are open and close on April 30.

Georgia Tech School of Electrical and Computer Engineering Professor Ali Adibi won the Innovation Award in Quantum Sensing and Nano Electronics and Photonics at the Society of Photo-Optical Instrumentation Engineers (SPIE) Photonics West Meeting in January. 

The award recognizes a member of Region 3 who has shared technical and professional abilities through teaching in industry, government, or in an institution of higher learning and in so doing has made an outstanding contribution to the electrotechnology student population.

Rincón-Mora, who is also a Fellow of the National Academy of Inventors, the Institute of Electrical and Electronics Engineers, and the Institution of Engineering and Technology, was selected out of the 24,000 members across Jamaica and the nine U.S. states that make up Region 3.  

“I grew up, studied, and worked in Florida and Georgia nearly all my life, dedicating my entire academic and professional career to learning, teaching, developing, and researching analog and power electronics, so receiving this award from IEEE in this region is a very special honor for me,” he said.

This is his second IEEE award in the last few months, having received the IEEE Atlanta Outstanding Educator Award in Nov. 2024.
Rincón-Mora has more than 25 years of service at Georgia Tech and the greater Atlanta area. He earned his M.S. in 1994 and Ph.D. in 1996 from Georgia Tech, and was inducted into Georgia Tech's Council of Outstanding Young Engineering Alumni in 2000. He worked for Texas Instruments in 1994–2003, was adjunct professor at ECE in 1999–2001, and has been a full-time professor  since 2001.
He is a recognized authority in the semiconductor industry in power supplies and energy harvesting.

Rincón-Mora pioneered the use of positive feedback loops to accelerate the response of low-dropout regulators and hysteretic control to stabilize and accelerate the response of switching power supplies. He developed and mastered techniques for rejecting and suppressing power-supply noise, allowing cell phones, tablets, and laptops power supplies to be more accurate, occupy less space, and consume less energy.

He also developed ground-breaking switched-inductor microchips that draw power from tiny fuel cells, vibrating piezoelectric transducers, and magnetically coupled coils. He pioneered ways of amplifying the power they draw by investing pre-damping energy into the system. He similarly developed photovoltaic and thermoelectric microchip technologies that draw more power from ambient light and heat and consume less energy. With these innovations, wireless microsystems draw more power from biological and ambient sources, so they can perform more functions across longer periods.

Rincón-Mora's current research focuses on the design and development of silicon-based microchips and microsystems that draw and condition power from tiny batteries, fuel cells, magnetically coupled coils, and generators that harness ambient energy from motion, light, temperature, and radiation to supply and sustain mobile, portable, and self-sustaining devices like wireless microsensors for biomedical, consumer, industrial, and military applications.

He will accept the award at the Region 3 Awards Dinner this in Charlotte, N.C.
 

He and his co-authors were recognized for their paper, “An Overview of Information-Theoretic Security and Privacy: Metrics, Limits and Applications,” which provides a comprehensive tutorial on foundational contributions to information-theoretic security.

The paper adopts an integrative perspective, detailing key security metrics such as secrecy and privacy, the methodology behind information-theoretic approaches, and the system design principles that emerge from them. It also explores the techniques that enable information-theoretic security to be applied in communication and computing systems.

Additionally, the authors emphasize the dual importance of fundamental limits and coding techniques in the design of secure communication systems.

Bloch, who also serves as the College of Engineer’s associate dean for Academic Affairs, is the inaugural winner of the award alongside his co-authors.

The IEEE Joy Thomas Tutorial Paper Award recognizes publications that expose subjects in information theory to a broad audience and stimulate interest and engagement in them.

Bloch came to Georgia Tech as a graduate student, earning his M.S. in electrical and computer engineering in 2003, and later a Ph.D. from Georgia Tech ECE in 2008. He joined Georgia Tech as faculty at the Lorraine campus in Metz, France in 2009, and in 2013, he moved to the main campus in Atlanta.

Prior to that he received the engineering degree from Supélec. In 2006, he received a Ph.D. in Engineering Science from the Université de Franche-Comté. Bloch spent a year as a postdoctoral research associate at the University of Notre Dame before returning to Georgia Tech in 2009. From January 2021 to January 2024,  Bloch was  the associate chair for Graduate Affairs in ECE.

RFID is a wireless system that uses radio waves to send information between devices and track objects. It’s become very important to the continued development of other crucial technologies like 5G wireless networks and virtual reality (VR).

Improvements to the wireless technology would lead to improved Internet of Things (IoT) devices with higher data rates and lower latency, as well as compact VR devices that accurately track location and orientation, facilitate real-time gesture recognition in virtual spaces, among other things.

RFID technology has the potential to improve gesture controls in virtual reality, tracking capabilities for the position and direction of drones and robots, and can be used in sensors to monitor temperature and air quality.

A pair of Georgia Tech School of Electrical and Computer Engineering (ECE) Ph.D. students were recently recognized for their work that is helping to bring this technology closer to becoming a reality.

Theodore Callis and Marvin Joshi received the Best Paper Award at the 2024 IEEE RFID Technology and Application Conference for their research on novel RFID architecture applications.

Their paper, “Novel mmWave/5G RFID Architectures for Next Generation of IoT Devices and VR Applications,” highlighted key advancements from the Professor Manos Tentzeris’ ATHENA lab, where they are using optics-inspired techniques and machine learning to push the limits of RFID technology.

This includes addressing challenges in long-range, wide-angle, and energy-efficient IoT designs, enabling precise localization and enhanced feasibility of mmID-based AR/VR applications

These designs bring together optics, machine learning, and RFID technology to make systems smarter and more efficient. Lenses, like those in glasses or microscopes, are added to RFIDs to sharpen signals, cover wider angles, and work over longer distances. Machine learning helps by making it easier to track locations, detect orientations, and recognize gestures, which can be used in AR/VR, robots, and drone tracking.

Callis and Joshi are both research assistant in the ATHENA lab. Callis’s current research focuses on additively manufactured RFID systems and integration of biological/chemical sensors with RFID systems.

Joshi’s current research interests focus on the integration of RADAR and artificial intelligence/machine learning with RF modules, specifically next generation RFIDs and mmIDs for ultra-long-range localization and tracking applications.

The College of Engineering (CoE) Staff Culture Advisory Council established the Culture Champion Awards Program to recognize staff members in each of the CoE schools who advocate for a positive and productive culture in their school and in the College. These individuals work to support and/or develop successful cultural practices and strive to make a difference.

Plaskett has been with ECE since 2013, where she is now a faculty support coordinator working with the Center for Signal and Information Processing and the Fiber-Wireless Integration and Networking (FiWIN) Center and with the digital signal processing and telecommunications technical interest groups. Plaskett is a floor manager, representing 5th floor interests to the management of the Centergy Building. She handles many issues and prevents them from rising to a level requiring faculty intervention. Plaskett does everything from managing workshops to coordinating sponsor visits to being the go-to person for over 50 graduate students.

Plaskett will serve as a member of the Georgia Tech Staff Council starting in 2022, and she serves on the Council's Employee Benefits and Compensation Committee. She is an active advocate for staff from the team and school level to the campus at large.

Prior to joining ECE, Plaskett was an administrative professional in the Scheller College of Business from 2010-2013, where she supported faculty and staff, including three department chairs. Before working at Georgia Tech, Plaskett was an administrative assistant at Kurt Salmon Associates, a management consulting firm now parented by Accenture. She holds a B.A. degree in Mathematics from Siena Heights University.

Plaskett completed the Georgia Tech ASPIRE Leadership program in 2019, and earlier this year, she received a Diversity, Equity, and Inclusion in the Workplace Certificate from the University of South Florida Corporate Training and Professional Education Division. 

The College of Engineering (CoE) Staff Culture Advisory Council established the Culture Champion Awards Program to recognize staff members in each of the CoE schools who advocate for a positive and productive culture in their school and in the College. These individuals work to support and/or develop successful cultural practices and strive to make a difference. 

Askew is ECE’s administrative manager and assistant to the School Chair, a position she has held since 2012. Prior to joining ECE, Askew worked in two other units at Georgia Tech. She was the project manager in the Office of the Vice Provost for International Initiatives from 2006-2012 and an administrative manager with the Yamacraw Initiative from 2001-2005. Askew and her family relocated to Georgia in 1996 during the Olympics, and she was employed as a banking officer/manager with SouthTrust Bank before joining Georgia Tech.

After high school, Askew joined the U.S. Army, where she served as a personnel management specialist. The military laid the foundation for Askew’s career path, where she used the opportunity to travel and meet people from different backgrounds, cultures, and experiences. It helped shape her views of the world and formulate strategies to help lead to a perfect union. Upon completing her military service, Askew relocated to California, where she was employed at Stanford University as an office manager in the Sponsored Projects Office for 13 years. Askew has also been able to earn her educational degrees and work in various administrative areas throughout her career.

Cadence Design Syst­ems, Inc. produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards. The company’s Diversity in Technology Scholarship supports underrepresented groups in their pursuit of careers in science, technology, engineering, and math (STEM) fields.

According to Khan, Tasneem’s work provides one of the most detailed and earliest accounts of reliability physics aspects of ferroelectric field-effect transistors for non-volatile memory applications. Her recent research introduces a novel characterization method which provides an understanding of the transport and the status of the ferroelectric during the FEFET’s operation. This could pave ways for ferroelectric devices to make the electrical hardware platform sustainable for data-intensive computing, leading to wide range of novel, ultra-fast and efficient intelligent applications.

Cadence scholarship winners are selected based on their impressive academic achievements, leadership, and drive to shape the world of technology. The scholarship works to build a culture that embraces inclusivity as well as diverse backgrounds, experiences, and ideas.

In addition to her Ph.D. research, Tasneem volunteers for IEEE Women in Engineering Society (WIE) and is currently a board member of the Atlanta chapter. She was an active member of the WIE Bangladesh chapter before coming to the United States as a graduate student. Tasneem is among few female students working in Georgia Tech's cleanrooms and hopes to increase female representation in the semiconductor industry through her research and extra-curricular activities.

All recipients of a Cadence scholarship are currently pursuing a technology-related degree, such as computer science, computer engineering, electrical engineering, and electronic engineering, and came highly recommended by their professors and advisors.

Cadence Design Syst­ems, Inc. produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards. The company’s Diversity in Technology Scholarship supports underrepresented groups in their pursuit of careers in science, technology, engineering, and math (STEM) fields.

Athena's research focuses on developing a fundamental understanding of the mechanism of neuromorphic devices and tailoring the device characteristics through material optimization and electrical testing engineering. She works at the Marcus Inorganic Cleanroom at Georgia Tech for semiconductor device fabrication and collaborates with industry partners to improve the performance of analog neuromorphic chips for deep learning applications.

“I am humbled to receive this scholarship, and it would not have been possible without the generous support from my advisor, Professor Eric M. Vogel,” said Athena. “I would also like to express my gratitude to Professor Samuel Graham, Jr. at the University of Maryland for his generous support. Finally, thanks to ECE for their support during my Ph.D.”

Outside the lab, Athena is active in Women in Electrical and Computer Engineering (WECE) and Women in Material Science and Engineering (WiMSE). She is actively involved in arranging outreach events to increase the involvement of women and minorities in technology, including a STEM workshop organized by WECE with support from the international rescue committee at Clarkston High School for students from refugee communities. She hopes to encourage minorities and females in STEM and semiconductor research.

All recipients of a Cadence scholarship are currently pursuing a technology-related degree, such as computer science, computer engineering, electrical engineering, and electronic engineering, and came highly recommended by their professors and advisors.

Cadence Design Syst­ems, Inc. produces software, hardware and silicon structures for designing integrated circuits, systems on chips (SoCs) and printed circuit boards. The company’s Diversity in Technology Scholarship supports underrepresented groups in their pursuit of careers in science, technology, engineering, and math (STEM) fields.

Nnamdi’s graduate research focuses on the intersection of bioinformatics, machine learning, and signal and image analysis with broad applications to clinical decision support. In addition to his Ph.D. research, Nnamdi serves as the African Graduate Students Connect (AGSC) vice president at Georgia Tech and is actively involved in organizing education and social events that are beneficial to all African graduate students.

Cadence scholarship winners are selected based on their impressive academic achievements, leadership, and drive to shape the world of technology. The scholarship works to build a culture that embraces inclusivity as well as diverse backgrounds, experiences, and ideas. All recipients of a Cadence scholarship currently pursuing a technology-related degree, such as computer science, computer engineering, electrical engineering, and electronic engineering, and came highly recommended by their professors and advisors.

The selective one-year fellowship is awarded to just three students around the world, with only one recipient typically coming from the Americas. The grant aims to promote, recognize, and support graduate master’s level study and research within the field of electron and ion-based devices.

Fernandes’s research focuses on the fabrication and characterization of novel and emerging semiconductor technologies for memory and logic applications, with an emphasis on ferroelectric materials for achieving high density and high performance.

With this fellowship, he aims to advance his research on the use of ferroelectric materials to enhance the performance and storage capabilities of 3D NAND-Flash, a key technology in modern non-volatile memory.

Fernandes, who is advised by ECE Associate Professor Asif Khan, is particularly passionate about exploring new materials and methods to optimize non-volatile memory technology, aiming to push the boundaries of performance, reliability, and scalability in this field.

His current projects seek to improve the endurance and data retention of memory devices by investigating new schemes and materials, with the goal of paving the way for the next generation of high-performance memory technology.

Chiplet-based systems are gaining exponential traction as a solution to these demands. However, because of multi-folded challenges, there is still much to be learned before chiplet-based systems, especially their die-die-to communication technologies, receive mainstream adoption.

Georgia Tech School of Electrical and Computer Engineering (ECE) third-year Ph.D. student, Srujan Penta won the Intel Outstanding Student Paper Award at the IEEE 74th Electronic Components and Technology Conference (ECTC) in Denver for his research on the performance-cost tradeoff of chiplet-based systems in 2D packaging technology.

“Just being able to present our work to so many bright minds at the conference and network with them was an enriching opportunity in my Ph.D. journey,” Penta said. “It is a cherry-on-top to receive the IEEE 74th ECTC Intel Outstanding Student Paper Award for this work.”

This paper demonstrated a parallel interface in a standard 2D package, as a cost-optimized alternative to the traditional chiplet interface and packaging architecture pairings, while providing moderate power and beachfront efficiency.

Penta designed interfaces in compliance with the Universal Chiplet Interconnect Express (UCIe), which is quickly becoming an industry standard.

He tested the interfaces for technical specifications of insertion loss and crosstalk, checking his findings against data from 3D EM simulations. At the same time, he evaluated 2D chiplet systems from a cost-based perspective against 2.5D systems to achieve a more complete understanding of the financial and technical trade-offs.

The research was completed in collaboration with Marvell Semiconductors, Inc. Penta was also aided by his advisor, ECE Professor and 3D Systems Packaging Research Center Director Muhannad Bakir.

Many of the world leaders in the semiconductor industry and academia come to ECTC each year.

Penta pursed a minor in Technology Innovation (TI:GER) from the Scheller School of Business. He was also named as one of the fifty global 2024 QUAD Fellows by the Institute of International Education (IIE). As part of the fellowship, he was invited to the White house and the U.S. State Department in Oct. 2024 to represent his home country, India.

Beyond his academic pursuits, he mentors students through the Office of Graduate Education at Georgia Tech and volunteers with the Out in Science, Technology, Engineering, and Mathematics (oSTEM) organization as a member of the Inclusivity, Diversity, Equity, and Accessibility (IDEA) team.

Music retrieval apps, for example, employ AI-powered search algorithms. While an update may technically improve the app by decreasing the average error rate of music retrieval, the subtle changes to the retrieval mechanism can cause a subjective performance degradation for the user.

This is known as software regression.

A Georgia Tech School of Electrical and Computer Engineering research team of postdoctoral research Fellow Mohit Prabhushankar, recent Ph.D. graduate Ryan Benkert, and Professor Ghassan AlRegib were the runners-up for the Best Paper Award at the 2024 IEEE International Conference on Big Data in Washington, D.C. Their research focused on minimizing subjective software regression from updates while simultaneously continuing to decrease objective errors.

The paper, “Targeting Negative Flips in Active Learning using Validation Sets,” aimed to train and update AI models using the Negative Flip Rate (NFR) metric.

NFR is a measure used in machine learning to quantify the rate at which a new model makes incorrect predictions on data points that were correctly predicted by a previous model.

The goal for the research is to have low NFR within the models with high algorithm accuracy. They were able to identify certain subsets in the training data that achieved this. The next step is creating a method that can proactively select these subsets.

The paper ultimately proposed to construct a Regression-ordered Subset Estimation (RoSE) using the data to consistently ensure accuracy of the AI model is high while reducing NFR.

Prabhushankar received his Ph.D. in electrical engineering from Georgia Tech in 2021. He is currently a postdoctoral research fellow in the Omni Lab for Intelligent Visual Engineering and Science (OLIVES). He is working in the fields of image processing,
machine learning, active learning, healthcare, and robust and explainable AI.

Benkert received his Ph.D. in electrical engineering from Georgia Tech in 2024. He is currently a deep learning software engineer at NVIDIA in Santa Clara, CA. His research interests are at the intersection of active learning, uncertainty estimation, and performance consistency in neural network learning. Prior to Georgia Tech, he received his B.Sc and M.Sc from the RWTH Aachen University in Germany.

Professor AlRegib is currently the John and Marilu McCarty Chair Professor ECE and directs OLIVES. He and his group work on robust and interpretable machine learning algorithms, uncertainty and trust, and human in the loop algorithms. The group has demonstrated their work on a wide range of applications such as Autonomous Systems, Medical Imaging, and Subsurface Imaging. The group is interested in advancing the fundamentals as well as the deployment of such systems in real-world scenarios. He has been issued several U.S. patents and invention disclosures. He is a Fellow of the IEEE.

Ferroelectric field effect transistors (FEFET) have emerged as a promising solution for logic and memory applications in next-generation edge computing, artificial intelligence, and enterprise cloud applications. The non-volatile memory technology harnesses electric polarization to store data in binary, and has been renowned for its speed, density, and ultra-low energy consumption.

Their widespread adoption, however, hinges on addressing critical reliability challenges.

Georgia Tech School of Electrical and Computer Engineering (ECE) third-year Ph.D. candidate Priyankka Ravikumar undertook the challenge of bringing clarity to one major reliability concerns in her paper, “First write pulse-induced interface damage in ferroelectric field-effect transistors.”

The research, completed in ECE associated professor Asif Khan’s lab, recently won the Best Student Paper Award at the 2024 IEEE International Integrated Reliability Workshop.

The research reported on a new phenomenon in FEFET, known as the first switch effect and explains the phenomenon’s origin. The findings reveal that the very first write operation on a FEFET contributes to nearly 50% of the total degradation seen over the device's lifetime.

The work is an important step towards understanding the fundamental drivers of degradation in FEFETs, laying the groundwork for developing innovative strategies to mitigate degradation, improve device performance, and facilitate the widespread adoption of the technology.

Ravikumar will be presenting this work at an invited talk next year at the 2025 IEEE International Reliability Physics Symposium.

Georgia Tech School of Electrical and Computer Engineering (ECE) Ph.D. graduate and current Stanford University research fellow Fabia Farlin Athena has made it her goal to make AI computing more efficient, while addressing financial accessibility.

Forbes honored her efforts by naming her to its annual North American 30 Under 30 Energy and Green Tech list. She was included alongside tech entrepreneurs, scientists, and public servants, all working to power a more sustainable future.

“I would like to extend my heartfelt thanks to my advisors, Prof. Eric M. Vogel and Prof. H.-S. Philip Wong, for their unwavering support and guidance,” Athena said. “I would also like to thank my mentors and collaborators at Precourt Institute for Energy at Stanford, IBM Research, and TSMC Corporate Research. Finally, I would like to thank Georgia Tech ECE for providing the platform to learn and grow during my Ph.D,”

Athena’s research focuses on developing emerging memory and logic technologies using oxide semiconductors and low dimensional materials for energy-efficient AI. Her current research focuses on high bandwidth oxide semiconductor gaincell memories.

She is in the midst of a prestigious three-year Stanford Energy Postdoctoral Fellowship sponsored by Stanford’s Precourt Institute for Energy and Doerr School of Sustainability, where she is working with electrical engineering professor H.-S. Philip Wong and materials science and engineering professor Alberto Salleo.

The fellowship aims to identify, develop, and connect the next generation of energy leaders — from science and engineering to policy and economics — to translate theoretical climate change solutions into tangible realities.

Athena is one of 14 Georgia Tech alumni, students, and faculty members named to the list, spanning nine categories. 
 

Georgia Tech School of Electrical and Computer Engineering Ph.D. student Nelson Sepúlveda-Ramos was recently recognized for his transistor research that hopes to lead to smaller, faster, and more reliable devices.

He won the Best Paper Award at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) for his presentation titled, “Using Pulsed-Mode Measurements of SiGe HBTs for Non-Destructive, Improved RF-SOA Estimation.”

The paper explores innovative methodologies to study the physics of Silicon-Germanium heterojunction bipolar transistors (SiGe HBTs) and introduces new approaches for testing and defining enhanced safe operating limits to optimize performance.

SiGe HBTs are a special type of transistor made by combining two materials: silicon, which is used in most electronics, and germanium, which helps improve performance. These transistors work faster than regular transistors and perform well in extreme conditions, making them great for things like satellite technology.

Transistors operate within safe limits, ensuring they don’t overheat or break down during use. Traditional testing methods use continuous stress to determine  these limits but must be applied cautiously to avoid damaging  the transistor, meaning its full power potential isn’t fully utilized.

Sepúlveda-Ramos’ research proposed a "pulsed-mode measurements" approach which applies very short bursts of stress allowing for the limits of the transistor to be pushed closer to the actual limit.

The ability to push transistors further will allow engineers to more reliably study their behavior at higher levels and deliver better performance, like faster processing or stronger signals without risking damage.

This will allow engineers to develop more efficient designs for electronics, potentially leading to improved technology for society, including internet speed, GPS accuracy, and reliability of tech in cars, planes, and space exploration.

BCICTS is the IEEE’s premier annual technical conference, drawing leading researchers, industry experts, and students from around the globe to showcase pioneering advancements in semiconductor technology.

Sepúlveda-Ramos completed the research along with fellow ECE Ph.D. student Harrison P. Lee, senior research engineer Jeffrey W. Teng, who is now with the Aerospace Corporation, and Professor John D. Cressler, as part of Cressler’s Silicon-Germanium Devices and Circuits research team.
 

The award highlights individuals who strive to build a better culture in their School and in the College. Recipients of the award are advocates for a positive and productive culture and truly strive to make a difference. The winners were announced at the College of Engineering Staff Engagement Day this fall.

Amwake provides strategic and tactical oversight for ECE’s research operations.

He is instrumental in guiding faculty through the grants and awards process. He assists with proposal preparation and submission including review of proposal documents and prepare budgets and budget justification for new proposals during the pre-award process.He also provides assistance to faculty over the span of their funded research projects.

Amwake was lauded by his colleagues for his leadership by example and the deep concern he has for those around him. Since joining the awards team as a grants administrator lead in 2022, he has helped to foster an environment of understanding. Having stepped into his current role at the beginning the 2024-2025 academic year, he’s helped to build a culture of confidence among his team.

Before his time at ECE he was at Florida State University, where he held various positions, including department manager for the Chemical and Biomedical Engineering Department and financial manager for the Department of Scientific Computing.
 

Shin has coupled his academic program with research in the Space Systems Design Laboratory and the Dynamics and Control System Laboratory at Georgia Tech, where he worked on various problems, including printed circuit boards (PCBs) that could withstand the harsh conditions of space. His expertise in resilient technology earned him coveted internships at Blue Origin and SpaceX, where he was a 2024 Matthew Isakowitz Fellow.

“James is a star. At Georgia Tech, he has artfully combined his skills and interests in electrical engineering and international affairs to address critical space policy issues," said Thomas González Roberts, a postdoctoral fellow in the Sam Nunn School of International Affairs. "He’s dedicated to working hard to develop hard-earned technical skills, but also not afraid to wade deep into big questions of international coordination, sustainability, and security in outer space.”

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Georgia Tech School of Electrical and Computer Engineering (ECE) Professor Larry Heck has been at the forefront of machine learning research since his time as an ECE Ph.D. student in the 1980s. Over his 30-year career, he has been a trailblazer in deep machine learning, pioneering algorithms for speech processing in the 1990s, web search relevance in the 2000s, and AI virtual assistants in the 2010s.

He helped develop several prominent programs, including Microsoft Cortana, Google Assistant, Viv Labs, and Samsung Bixby.

His influential research on deep learning for web search was recently honored with the Test of Time Award by the Conference on Information and Knowledge Management (CIKM). This prestigious award recognizes CIKM papers published over a decade ago that have made a significant and lasting impact on the research community.

Heck received the award for his 2013 paper, “Learning deep structured semantic models for web search using clickthrough data.” It is one of the earliest publications in deep learning for web search and resulted in one of the most successful and impactful innovations in Microsoft’s Bing Search engine.

“This paper represents a fantastic collaboration between product engineers and deep learning research scientists and was an early example of the power of big data (100M+ daily search clicks) and massive computing,” Heck said.

The research included innovations in training a deep learning search relevance engine with a discriminative objective function over clickthrough data. Clickthrough data measures how often users click on a document or advertisement link relative to how many times it was viewed.

Heck’s paper was not only one of the earliest in deep learning for web search, but it was also the first to differentiate between good and bad clicks in training a web search relevance model.

Heck has a joint appointment with the School of Interactive Computing and is the chief scientist of Tech AI, executive director of the Machine Learning Center. He holds the Rhesa S. Farmer Advanced Computing Concepts Chair and is a Georgia Research Alliance Eminent Scholar.

He had over 30 years of industry research experience before returning to his alma mater Georgia Tech in 2021. This included positions at many industry leaders such as Google, Microsoft, Yahoo!, and Samsung. He currently directs the AI Virtual Assistant (AVA) Lab which focuses on creating the next generation of AI virtual assistants with conversational AI.

ECE professor Suman Datta previously won the Test of Time Award in 2022.

The award recognizes lifetime research contributions to the U.S. semiconductor industry by university faculty. Since being established in 1995, only 50 faculty members from top universities around the U.S. have won the award.

"Professors Suman Datta and Michael Flynn join an illustrious group of past award winners who have made significant contributions to the semiconductor industry,” SRC President and CEO Todd Younkin said in a press release. “Their groundbreaking research and its translation into the commercial domain continue to drive innovation and excellence in our field.”

Datta, who is the Joseph M. Pettit Chair of Advanced Computing in the Georgia Tech School of Electrical and Computer Engineering (ECE) and a Georgia Research Alliance (GRA) Eminent Scholar, is just the second Georgia Tech faculty member to win the award. Former ECE professor Jim Meindl won the award in 1999.

He’s renowned for the design, fabrication, characterization, and compact modeling of nanoelectronic devices, as well as their applications in circuits for next-generation, energy-efficient, and high-performance computing.

Since coming to ECE in the Fall of 2022, Datta, who also has a joint appointment with the School of Materials Science and Engineering, has directed the Semiconductor Technology Advanced Research (STAR) Laboratory. The STAR research group focuses on novel semiconductor devices that enable new compute models such as in-memory compute, brain-inspired compute, and cryogenic compute.

Datta’s research is primarily funded by the National Science Foundation (NSF), Defense Advanced Research Projects Agency (DARPA), Department of Energy, Defense Threat Reduction Agency, Semiconductor Research Corporation, and semiconductor companies like Intel, Micron, Samsung Electronics, Applied Materials, EMD Performance Materials.

Datta had established himself as a recognized leader in semiconductor innovation, with over 20 years of experience before joining ECE

From 1999-2007, he was in the Advanced Transistor Group at Intel Corporation, where he led the research and development efforts for several generations of high-performance logic transistors such as high-k/metal gate, Tri-gate, and strained channel complementary metal-oxide-semiconductor transistors.

He then joined academia at the Pennsylvania State University (PSU), where he was a professor of electrical engineering until 2015. His group at PSU pioneered advances in compound semiconductor-based quantum-well field effect transistors and tunneling field effect transistors.

Datta continued to be at the forefront of semiconductor innovation during his time as the Stinson Endowed Chair Professor of Nanotechnology in the Electrical Engineering Department at the University of Notre Dame from 2015-2022. There, he was the director of several multi-university research centers.

Most notably, one of those centers, the Extremely Energy Efficient Collective Electronics (EXCEL), sponsored by NSF, explored an alternate computing hardware that leverages continuous-time dynamics of emerging devices to execute optimization, learning, and inference tasks.

Additionally, he led the ASCENT project (Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies) funded by SRC’s Joint University Microelectronics Program.

His work has resulted in over 475 journal and refereed conference papers and more than 187 issued patents related to semiconductor devices.

He’s received several other notable distinctions for his research, including being named a Fellow of IEEE and the National Academy of Inventors.

Datta received his undergraduate degree in electrical engineering from the Indian Institute of Technology in Kanpur, India, and his Ph.D. degree in electrical and computer engineering from the University of Cincinnati. 
 

His research and accomplishments have helped him to become a nationally recognized expert in biomedical imaging instrumentation and nanoagents for imaging and therapy.

The IEEE Ultrasonics, Ferroelectrics, and Frequency Control Society (UFFC) recently celebrated his achievements and impact in the ultrasonics field by honoring him with the prestigious Rayleigh Award at the organization’s annual meeting in Taipei, Taiwan.

The award, which is the IEEE UFFC’s highest accolade, recognizes sustained outstanding achievements in technical innovations, research, education, publications, and professional contributions over a span of more than 25 years.

Emelianov, a Georgia Research Alliance Eminent Scholar, received the award for his seminal contributions to elasticity imaging, ultrasound-guided photoacoustic imaging, and theranostic contrast agents.

“The Rayleigh award is an honor that highlights the transformative potential of biomedical ultrasound, and it reflects collaborative efforts of my trainees, colleagues, and collaborators who have contributed to advancing diagnostic ultrasound imaging and image-guided therapy,” Emelianov said.

His work has pioneered several techniques in those research areas and are capable of detecting and diagnosing cancer and other pathologies, assisting treatment planning, and enhancing image-guided therapy and monitoring of the treatment outcome. He has also developed approaches for image-guided molecular therapy and therapeutic applications of ultrasound and electromagnetic energy.

Emelianov, holds a joint appointment in the School of Electrical and Computer Engineering and the Wallace H. Coulter Department of Biomedical Engineering (BME). He is also appointed at the Emory University School of Medicine, where he is affiliated with Winship Cancer Institute, Department of Radiology, and other clinical units

He’s authored of over 250 archival publications including peer-reviewed research articles, invited reviews and book chapters, and more than 550 proceedings, abstracts, and presentations.

Currently, he runs the Ultrasound Imaging and Therapeutics Research Laboratory, with a research focuses on cancer and other disease imagining, ranging from molecular imaging, functional imaging, and tissue differentiation to drug delivery and release, image-guided surgery, and intervention.

Emelianov was recently named the co-director of the Children’s Healthcare of Atlanta Pediatric Technology Center (PTC). In this role, he oversees a unique partnership that supports interdisciplinary research among clinicians, engineers, and scientists from Georgia Tech, Children’s, and Emory University. The goal is to harness the power of artificial intelligence, data science, and cutting-edge medical devices to address the most pressing challenges in pediatric healthcare.

In recognition of his groundbreaking contributions to the field, Emelianov has received several other recognitions, including Fellow of the American Institute for Medical and Biological Engineering (AIMBE), Institute of Electrical and Electronics Engineers (IEEE), Acoustical Society of America (OSA), and Society of Photographic Instrumentation Engineers (SPIE).

Emelianov has been with ECE since 2015. He received his undergraduate and graduate education from Moscow State University. He then completed his post-graduate work at the University of Michigan.

From 2002 to 2015, Emelianov was a faculty member in the BME and ECE Departments at the University of Texas at Austin and Department of Imaging Physics at the University of Texas M.D. Anderson Cancer Center.

The award recognizes a member of the Atlanta community who, through service to IEEE or other professional and technical organizations, has made an outstanding contribution to the electrotechnology profession.

Rincon-Mora, who is also a Fellow of the National Academy of Inventors, the Institute of Electrical and Electronics Engineers, and the Institution of Engineering and Technology, won for ground-breaking developments to power regulation and energy harvesting technologies, and outstanding contributions to analog microcircuit education.

Rincon-Mora has more than 25 years of service at Georgia Tech and the greater Atlanta area. He earned his M.S. in 1994 and Ph.D. in 1996 from Georgia Tech, and was inducted into Georgia Tech's Council of Outstanding Young Engineering Alumni in 2000. He worked for Texas Instruments in 1994–2003, was Adjunct Professor at ECE in 1999–2001, and has been a full-time professor at Georgia Tech since 2001.

He is a recognized authority in the semiconductor industry in power supplies and energy harvesting.

Rincon-Mora pioneered the use of positive feedback loops to accelerate the response of low-dropout regulators and hysteretic control to stabilize and accelerate the response of switching power supplies. He developed and mastered techniques for rejecting and suppressing power-supply noise, allowing cell phones, tablets, and laptops power supplies to be more accurate, occupy less space, and consume less energy.

He also developed ground-breaking switched-inductor microchips that draw power from tiny fuel cells, vibrating piezoelectric transducers, and magnetically coupled coils. He pioneered ways of amplifying the power they draw by investing pre-damping energy into the system. He similarly developed photovoltaic and thermoelectric microchip technologies that draw more power from ambient light and heat and consume less energy. With these innovations, wireless microsystems draw more power from biological and ambient sources, so they can perform more functions across longer periods.

He's taught ECE 3040 Microelectronic Circuits, ECE 3400 Analog Electronics, ECE 4430 Analog Integrated Circuits, ECE 6412 Analog IC Design, and ECE 6445 Power IC Design at Georgia Tech and professional short courses on analog, power, and energy integrated-circuit design for Intel, ON Semiconductor, Dialog Semiconductor, Cypress Semiconductor, Integrated Device Tech., Dolphin Design, RF Micro-Devices, Space & Naval Warfare Syst. Command, Toko Inc., Spyro Tech., and others.

His scholarly output includes 12 books, 8 handbooks, 4 book chapters, 44 patents, over 200 articles, 25 educational videos, and over 26 commercial power-chip products released to production.

Rincón-Mora's current research focuses on the design and development of silicon-based microchips and microsystems that draw and condition power from tiny batteries, fuel cells, magnetically coupled coils, and generators that harness ambient energy from motion, light, temperature, and radiation to supply and sustain mobile, portable, and self-sustaining devices like wireless microsensors for biomedical, consumer, industrial, and military applications.

He’s received a number of other awards for his work.

He’s been recognized with the National Hispanic in Technology Award from the Society of Hispanic Professional Engineers, Charles E. Perry Visionary Award from Florida International University, Three-Year Patent Award from Texas Instruments, Orgullo Hispano Award and Hispanic Heritage Award from Robins Air Force Base, a State of California Commendation Certificate from Lieutenant Governor Cruz M. Bustamante, and the IEEE Service Award, among many others.

It was highlighted by Ph.D. student Seung Yoon Lee winning the third prize of Student Paper Competition for his research titled, “Highly Integrated mmWave Antenna-on-Chip Arrays Using Substrate-Integrated Air Cavities.”

The paper was selected out of 172 accepted papers at the conference.

It presents the design, fabrication, and characterization of a 60 gigahertz (109 hertz) beamforming array for 6G high data-rate wireless systems. Specially, it introduces mmWave 1×8 on-chip miniaturized cavity antenna arrays with high efficiency and reduced mutual coupling, leading to better connectivity.

The proposed silicon-based antenna offers the potential for future wireless system-on-a-chip (SoC) applications better equipped to handle high data throughput. Microfabrication of the proposed antennas and cavities was performed at Georgia Tech cleanroom facility.

Lee completed the research in Associate Professor Nima Ghalichechian’s mmWave Antennas and Arrays Laboratory.

This is the latest of many research recognitions for Lee. He most recently received the IEEE Antenna and Propagation Society grant for the development of a highly efficient on-chip antenna array, in hopes of addressing growing global mobile video traffic.

Lee has also published seven peer-reviewed journal articles, 14 international conference papers, and is the inventor of 19 patents.

Three other ECE research groups presented research at the conference: Professor Morris Cohen’s Low Frequency Radio Group, Professor Visvesh Sathe’s Processing Systems Lab, and Professor Manos Tentzeris’ ATHENA Research Group.
 

Sanchez Perez, who recently started as an assistant professor at his undergraduate alma mater, the University of Puerto Rico at Mayaguez (UPRM), conducted the research in Professor Omer Inan’s Inan Research Lab. It’s the second consecutive year a researcher from Inan’s lab won the Best Paper Award from the conference.

The award-winning research introduced a novel approach for the continuous and non-invasive assessment of pleural effusion (PE) using transthoracic bioimpedance continuously measured at multiple frequencies.

PE, which affects over 1.5 million patients in the U.S., is the accumulation of excess fluid around the lungs, compressing them, increasing the risk of developing infections, and leading to respiratory distress.

Current PE assessments remain limited to sporadic measurements due to their cost, availability, or radiation exposure. This results in the unsatisfactory prognosis and assessment of symptoms for patients.

Sanchez Perez’s approach addresses the problem by exploiting the information embedded in the multi-frequency bioimpedance signals at multiple resolutions, namely the baseline and respiratory components.

He achieved this by extracting six fluid-tracking surrogates and found them to be strongly and significantly correlated to the infused pleural fluid in a porcine animal model of bilateral PE. The early results have promising, paving for continued research and testing.

Ultimately, the research may enable continuous and convenient respiratory monitoring in at-home and uncontrolled clinical settings, which can prevent acute deteriorations, improve treatment outcomes, and help patients.

The technology also has future applications in assessing many diseases including congestive heart failure, liver cirrhosis, and pneumonia.

Sanchez-Perez’s blended his research at ECE with his minor, biomedical engineering. It focused on investigating novel cardiopulmonary monitoring technologies, with a special focus on applications to clinical and acute-care settings.

It helped him to achieve his dream of returning to UPRM as a faculty member, where he’ll now continue doing innovative research with hopes of continuing to help people and achieve better medical outcomes.

Ph.D. candidate Zishen Wan won the Best Presentation Award, while fourth-year electrical engineering student Avanish Narumanch placed top three in the Undergraduate Research Awards.

Wan presented his research, “Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations,” which aims to improve AI systems' ability to perceive and reason by disentangling complex sensory signals.

"The research enhances AI systems' ability to disentangle complex sensory signals, which is critical for advancing perception and reasoning in future cognitive AI systems."

Along with the award, Wan was one of just four students selected to present their research to the SRC director and keynote speaker.

The research presents a heterogeneous 3D integrated in-memory compute engine to breakdown complex object representations. The technology is able to store and recognize complex patterns through holographic perceptual representations, which holds detailed information similar to that of a hologram.

This process can store a lot of information in a way that mimics human perception.

The system uses a technology called "memristors," which are tiny devices that can remember and adjust their electrical resistance depending on the task. These memristors have built-in stochasticity or non-volatility, combined with volatile memory as a heterogeneous system, enabling more effective simulation of natural systems and better handling of uncertainty in computing.

The results have been very promising. Wan’s design has shown a five-order magnitude increase in factorization capacity. It’s also more efficient, packing in five and a half times more computing power into almost six times less space than 2D designs, while using 20 percent less energy.

Narumanch was recognized for his research on ways to achieve faster and more energy-efficient memory devices. It focused on spintronic memory devices, which are non-volatile, low-power, and scalable electronic devices that use electron spin to store information.

The goal of the project was to reduce switching time and energy consumption without sacrificing reliability.

Both students completed the research through the JUMP 2.0 COCOSYS Center.

Wan’s work was in collaboration with senior research engineer Mohamed Ibrahim, Associate Professor Tushar Krishna, and Professor Arijit Raychowdury, along with fellow ECE Ph.D. students Che-Kai Liu (co-first author), Hanchen Yang, and Samuel Spetalnick.

This is the latest of many awards his work has received, which include being named a 2023 Machine Learning and Systems Rising Star and 2024 Cyber-Physical Systems Rising Star.

Narumanch worked on his research under the guidance of ECE Ph.D. candidate Md Nahid Haque Shazon, who works in ECE Professor Azad Naeemi’s Nanoelectronics Research Lab.

SRC TECHCON is the annual flagship technical conference hosted by the SRC. The conference draws top researchers, scientists, and a large field of students from across the United States and world to present cutting-edge research in the field of semiconductor electronics.

Wang is pursuing her Ph.D. in computer science, working in Assistant Professor Divya Mahajan’s Infrastructure and Architecture Research Lab in the School of Electrical and Computer Engineering (ECE).

She was selected for her research on advancing deep learning infrastructure to meet the computational needs to run increasingly complex large language models (LLM). LLMs are a type of computational model designed for natural language processing tasks such as language generation. ChatGPT is a common example of an LLM.

The power of many LLMs have surpassed the computational and memory capabilities of single accelerators. This has made a distributed approach necessary train and execute these models.

Wang’s research proposes a state-of-the-art in-distributed deep learning infrastructure that co-optimizes architecture, network, and device placement strategies.

Each of these aspects play a fundamental role in executing distributed deep learning, involving trade-offs in computational efficiency, communication costs, and memory footprint, according to Wang.

The goal is efficiency, according to Wang.With so many variables and a wide range of outcomes, efficiency is very important to finding the best possible combinations of conditions to run different LLMs.

“Ultimately, my goal is to develop systems that not only make deep learning more resource-efficient but also foster broader access across diverse populations and industries, promoting equitable and sustainable advancements in AI infrastructure design,” she said.

NSERC funds visionaries, explorers and innovators who are searching for the scientific and technical breakthroughs that will benefit Canada, according to the Council’s website.

The Canada Graduate Scholarship offers three years of financial support to a select group of highly accomplished Canadian graduate students.

Wang received her B.S. in computer engineering from the University of British Columbia.

The award-winning paper, “HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond,” introduces an open-source infrastructure that simplifies the contribution and sharing of hardware designs.

This platform allows developers to submit their designs to a common pool, making it easy for machine learning practitioners to access the data they need to train their algorithms, ultimately driving advancements in hardware design.

The framework addresses a major challenge in applying machine learning to chip design:the scarcity of high-quality training data. By being open-source, HLSFactory encourages a wide range of contributions from the community, creating a richer dataset for researchers and developers.

“HLSFactory creates unified platform that the entire community can leverage to drive more scientific discoveries and improve design outcomes,” said Hao.

The software was developed through Hao's Software/Hardware Co-Design Lab.

ECE Ph.D. candidate Stefan Abi-Karam was the lead author on the paper. Abi-Karam previously won the Community Award at the 33rd International Conference on Field-Programmable Logic and Applications (FPL) 2023, for his work on “GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization.” The award recognized his contributions to the open-source community, underscoringthe group’s dedication to open-source tools and hardware design, according to Hao.

ECE Ph.D. candidates Rishov Sarkar and Hanqiu Chen also contributed to the paper, alongside collaborators Allison Seigler, Sean Lowe, Zhigang Wei, Nanditha Rao, and Lizy Kurian John from the University of Texas at Austin, and Aman Arora from Arizona State University.

Hao, who joined the Georgia Tech ECE faculty in 2022, specializes in efficient hardware design and machine learning algorithms. Her research focuses on reconfigurable, high-efficiency computing and developing practical electronic design automation tools. She has previously been recognized with several prestigious awards, including the NSF CAREER Award and the Intel Rising Star Faculty Award, for her groundbreaking work in hardware design research.
 

The group reports to the DOE’s Assistant Secretary for Electricity and consists of 40 members representing a cross-section of energy stakeholders, including from utilities, industry, regional entities, industry, cyber security experts, natural gas sector and others.

Divan is the sole representative from academia and advanced research on the EAC.

“I am honored by this appointment to the EAC and look forward to providing inputs to ensure that the U.S.takes a holistic view on the highly disruptive energy transition, one that provides abundant, economical and equitable energy to meet our near-term and long-term energy needs, but where our sustainability and climate goals are also met,” Divan said. “Rapid development, deployment and scaling of globally competitive new technologies are a key element of this. I look forward to working with the DOE and other EAC members on these critical issues over the next two years.”

During his two-year term, Divan will advise the DOE on key issues related to current and future electric grid resilience, security, reliability, sector interdependence, and policy issues of concern.

The EAC periodically reviews and makes recommendations on DOE electric grid-related programs and initiatives, including electricity-related research and development programs and modeling efforts. The committee also helps to identify emerging issues, address the growing interdependence of and risk to critical and defense critical electric infrastructure, and help ensure national policy and programs are aligned to manage and prosper from the ongoing energy transition.

Divan is highly-respected for his expertise, having been active in grid related research and entrepreneurship for over 40 years. He is well-recognized in the field, including as a member of the U.S. National Academy of Engineering, the National Academy of Engineering’s Transformative Science & Technology Committee, a past member of the NASEM Board on Energy and Environmental Systems, the 2021 NASEM Committee on the Future of Electric Power in the US, and is the recipient of the 2024 IEEE Power Engineering Medal.

His research focuses on advanced power electronics and grid related research, and the acceleration of deep-tech to market, especially in grid related areas.

He is also the coauthor of a new book – ‘Energy 2040: Aligning Innovation, Economics and Decarbonization’ by Divan and Sharma, that provides a holistic view of the energy transition, identifies major challenges (especially with the grid), and shows a path forward. 

His award-winning poster, “Fabrication and Detailed Analysis of 22.0% Rear Junction Double-side TOPCon Solar Cell with Front SiOx/Polysilicon Selective Emitter” presents a novel cell design and fabrication process to make next-generation, low-cost, high-efficiency silicon solar cells.

This method utilizes Tunnel Oxide Passivated Contacts (TOPCON) technology, which uses a thin layer of tunnel oxide to reduce diffusion and metal-induced recombination in silicon solar cells to significantly enhance their efficiency.

The approach has the potential to make solar electricity significantly cheaper than fossil fuels, possibly by two to three times, according to Choi.

"Winning this award at IEEE PVSC was a tremendous honor,” he said. “My future research will focus on optimizing solar cell architectures to enhance performance, aiming to make sustainable energy more accessible."

PVSC is the signature event in the solar power technology and the market sector where over 2,000 scientists and engineers at the forefront of photovoltaic research and development gather.

The research was conducted in ECE’s University Center of Excellence for Photovoltaics, under Choi’s advisor ECE regent’s professor Ajeet Rohatgi.

The project was supported by the U.S Department of Energy’s Office of Energy Efficiency and Renewable Energy (EERE) under Solar Energy Technologies Office (SETO).

Choi received his B.S. and M.S. degree in Electrical and Computer Engineering from Georgia Tech and is currently pursuing a Ph.D. with ECE. His photovoltaics research was previously recognized with the Best Student Paper Award at the 49th IEEE Photovoltaics Specialists Conference in 2022.

The global fellowship program is a joint initiative of the Australian, Indian, Japan, and United States governments to build ties among the next generation of scientists and technologists.

It sponsors exceptional master's and doctoral students who study science, technology, engineering, and mathematics (STEM), building a network of experts committed to advancing innovation and collaboration in the private, public, and academic sectors.

“I anticipate leveraging my experience as a Quad Fellow and connections within the Quad community towards my long-term goals of democratizing the semiconductor chip supply chain and providing education and employment opportunities to individuals from marginalized communities in STEM,” Penta said.

Penta’s doctoral research, conducted under ECE professor Muhannad Bakir in his Integrated 3D Systems Group, aims to bridge the performance-cost trade-off gap between standardized chiplet-based systems that perform better than a traditional system-on-a-chip.

He was one of 50 students to receive the fellowship world-wide, including four recipients from Georgia Tech, Penta being the only recipient from ECE.

“I am grateful to my family, friends, peers, the School of ECE and my advisor, Muhannad Bakir who supported me in the application process,” Penta said. “I am excited about this unique opportunity to connect with world leaders in the key roles for the development of the Indo-Pacific regions, specifically the semiconductor landscape."

Penta is from Hyderabad, India, and graduated with a B.E. in electrical and electronics engineering from the Birla Institute of Technology and Science (BITS), Pilani, India.

He worked on state-of-the-art transistor technologies as a process design kit engineer at Samsung Semiconductors in Bengaluru, India, before pursuing his Ph.D. at Georgia Tech in 2022.

Penta is also committed to furthering his understanding of the business side of engineering. He is part of the Technology Innovation: Generating Economic Results (TI:GER) program at the Georgia Tech Scheller School of Business, where he learns about the entrepreneurial strategies for technical ideas and innovations.
 

“You can’t connect the dots looking forward; you can only connect them looking backwards.” These words, famously attributed to Steve Jobs, address the broad truth that only through intentional reflection and examination can we learn from the past.

With this in mind, an interdisciplinary research team comprised of engineers and historians from the Georgia Institute of Technology, the University of Houston, and the University of Minnesota are hoping to shape the future of electric power grids by studying and cataloguing the field’s robust history during a two-year study funded by the Alfred P. Sloan Foundation.

“While electrical engineering is at the forefront of many of today’s technological advancements, a critical step in the process of innovative and cutting-edge research is working to understand the past,” said Dan Molzahn, assistant professor in the Georgia Tech School of Electrical and Computer Engineering and the project’s principal investigator.

The group’s project, "Algorithms and Power Systems Architecture: Using Historical Analysis to Envision a Sustainable Future", emerges out of the Sloan Foundation’s emphasis to award historical scholarship projects that look to understand the contemporary context of scientific research and inform current and future research and policy practices. The study will examine the relatively invisible, yet central, role of the algorithms 20th-century engineers developed to provide optimization and control of the electric power grid and the ways in which these algorithms might impact the cleaner grid of the future.

“Clarifying how invisible technologies [like algorithms] became established in large and complex power systems is the ultimate goal of the project,” said Molzahn. “As algorithms became thoroughly naturalized within power systems architecture, they set the boundaries and established the scope of possibility; this can restrict innovation across the technology spectrum.”

The research team — two historians and two engineers — represents an innovative alliance of technical, historical, and public policy approaches. In addition to Molzahn, the team includes Sairaj Dhople, associate professor of electrical and computer engineering at the University of Minnesota (UMN); Julie Cohn, a research historian at the Center for Public History at the University of Houston (UH); and Monica Perales, associate professor of history and director of the Center for Public History at UH.

The project comes at a time when power grids are in the throes of new demands and transformation. As a result of aging technology and regulatory structures that impede upgrades of essential power infrastructure, current grids are inadequate in integrating renewable energy sources at the scale the market requires. Energy providers and researchers are also looking for ways to guard power systems against cyber assaults, as well as against an increased risk of extreme weather events due to climate change — the average overall duration of power interruptions due to weather in the U.S. doubled since 2015, according to the U.S. Department of Energy.

“The opportunities and challenges of widespread electrification are front and center for the public. Debates about climate change, opposition to large-scale energy infrastructure, and periodic weather-related power outages appear in the news regularly,” said Cohn, who is an expert on the development of the North American electric power grid and author of the book “The Grid” on the topic.

A particularly important part of the project is collecting the oral history of individuals who were instrumental in the development, adoption, and application of algorithms in North America. The team will train history and engineering graduate students to conduct approximately 50 interviews with members of the National Academy of Engineering, IEEE Fellows, and prominent power systems engineers.

“The interviews themselves will be the best way to make this project relevant for a non-technical audience,” said Perales, an expert on oral history methods. “When you hear a person tell their story about why they became interested in working on the power system, it is often more than a ‘technical’ story. They offer insight into the ‘why’, which is always compelling.”

The interviews will be archived at UH and the IEEE History Center, and will eventually be made available to other researchers and the public. The team will use the interviews as important source information to produce a podcast that interprets the highly technical history of algorithms and power systems architecture for a broad audience, especially those interested in climate change and sustainability.

The completed history will then be leveraged in engineering courses taught by Molzahn at Tech and Dhople at the UM with the hope that other institutions will utilize the team’s findings to provide appropriate historical context in their power engineering courses.

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LISTEN NOW!
Discovering Power in the Past: The Algorithms and Power Systems Architecture Project from the University of Houston's "Public Historians at Work" podcast.

None more ever-present than Professor Aaron Lanterman, who will be participating in or leading six sessions over the four-day event.

The sessions will be a mixture of talks and panels covering video games, robotics and the science of music, as well as providing hands-on demonstrations and doing Q&As with the audience.

ECE graduate-turned Georgia Tech Research Institute (GTRI) senior esearch engineer Sean Wilson will also give a talk titled, “The Robotarium: Democratizing Access to Robotics.”

Stepping away from the science and into the sonics, Friday night Professor Larry Heck will be there on the trumpet with his band The Atlanta Swing Orchestra.

They’ll play their swing jazz music for convention-goers in the Hyatt Regency Centennial Ballroom II-IV starting at 8:30 p.m.

Georgia Tech and ECE has had a presence at Dragon Con dating back several years. Lanterman has attended Dragon Con since 2001 and has spoken at it several times in the past. This year will be his first year speaking since 2021.

ECE Professor John Cressler also gave a talk in 2016 titled, “The Many Miracles of the Microelectronics Revolution.”

Starting in 1987, Dragon Con has grown into one of the largest pop culture conventions in the U.S., attracting over 85,000 people in 2019. It showcases the latest in science fiction & fantasy, gaming, comics, literature, art, music, and film.

Find the schedule for the ECE-involved programming below:

Friday, August 30, 2024

Building Custom Controllers
Time: 2:30 p.m. 
Location: Westin Augusta A-B
Speaker: Aaron Lanterman
Arcade games like Asteroid, Inferno, & Defender require non-standard controller setups, & those can be hard to locate. Dr. Lanterman will talk about the work he & some of his students have done to make these kinds of controllers. There will also be time for a hands-on demo and Q&A.

Classic Gaming Hardware
Time: 4:00 p.m. 
Location: Westin Augusta A-B
Speaker: Aaron Lanterman
From the 2600 to the Switch, the Atari 800 to the Amiga, 2D to 3D, player-missile graphics to FMV - dive deep into the CPUs, GPUs, & system architectures that ran your favorite games. Although accessible to a non-technical audience, some assembly code may be required.

Hand-on with Classic Video Game Hardware
Time: 5:30 p.m. 
Location: Westin Augusta A-B
Speaker: Aaron Lanterman
You ever want to recapture (or maybe capture for the first time) the magic of playing on a retro console? Ever want to get some hands-on experience with a custom-made controller for a game rig? Now's your chance!

Sunday, Septemner 1, 2024

Making and STEM Education (Panel)
Time: 10:00 a.m. 
Location: Courtland Grand Valdosta
Speaker: Aaron Lanterman
This is a panel discussion from experienced Makers. The discussion will center around how the Maker Movement inspires young people to explore STEM Education and technical careers.

Resurrecting Vintage Synthesizers & Computers: Shall We Play a Game? 
Time: 1:00 p.m. 
Location: Courtland Grand Atlanta 1-2
Speaker: Aaron Lanterman
Come flip switches on the IMSAI 8080 computer from Wargames or play tunes on synths like the 1970s Moogs. Learn to decipher schematics, replace exploded capacitors, safely discharge CRTs. Fabricate new electronics to meld with the old: PCB layout, front-panel fabrication, custom arcade controllers.

The Robotarium: Democratizing Access to Robotics
Time: 4:00 p.m. 
Location: Courtland Grand Atlanta 1-2
Speaker: Sean Wilson
Join Georgia Tech's Dr. Sean Wilson as he shares how the Robotarium provides a remotely accessible swarm robotics research platform to anyone in the world free of charge and demonstrates how you can control the robots yourself!

Monday, September 2, 2024

The Science of Music (Panel)
Time: 1:00 p.m. 
Location: Hilton 209-211
Speaker: Aaron Lanterman
Science lurks behind a lot of music, from the harmonics of overtones to the vibration of strings and air columns. We'll cover synths, singing, and more.
 

The first award was the IEEE Modeling and Control Technical Achievement Award for her contributions to modeling and control of multilevel converters for medium- and high-power energy conversion systems.

The award honors innovators and researchers who have made outstanding and sustained technical contributions to the advancement of power electronics in modeling and control. She will be presented with the award at the IEEE Energy Conversion Congress and Exposition this October in Phoenix.

Saeedifard also won the IEEE Bimal Bose Award for Industrial Electronics Applications in Energy Systems.

She received the honor for  her work on renewable energy integration and transmission, as well as protection and stability analysis of multi-terminal HVDC grids.

The award recognizes a young researcher who has made significant contributions to the advancement of energy systems through industrial electronics applications. The award will be presented to her at the IEEE Industrial Electronics Conference this November in Chicago, where she is also one of the plenary speakers.

Saeedifard joined ECE as an assistant professor in spring 2014, specializing in power electronics and modular energy conversion systems for both terrestrial and mobile power systems.

Her research has garnered numerous national and international awards, including several prize paper awards for her impactful IEEE Transactions publications, as well as being recognized as an IEEE Fellow by the Power Electronics Society in 2022. She also serves as co-editor-in-chief of IEEE Transactions on Power Electronics.

She was recently appointed a Ken Byers Professor in ECE and serves as the School’s inaugural director of Faculty Evaluation and Recognition.

Since the start of her academic career in 2010, she has successfully advised and graduated 13 Ph.D. students and five M.S. students.

The merit-based fellowship is given to exceptional graduate students in honor of College of Engineering graduate Herbert P. Haley (ME 1933).

VO2 is a phase change material that has the capability to change from behaving like an insulator to behaving like a conductor by applying temperature, electric field, or stress.

Disharoon’s research aims to harness the power of this material to improve modern high-speed communication systems that must deal with the large losses when transmitting at extremely high frequency such as millimeter wave (mmWave).

He also plans to demonstrate its protection capabilities as an energy selective surface. By selectively placing VO2, the surface allows low-power waves to transmit through unaffected while also being able to quickly transition to a conductive state and reject high-power waves.

This can help protect critical communication infrastructure from unintentional interference sources and malicious systems.

“I am happy to be selected for the fellowship as it continues to enable me to purse interesting research that has the potential to revolutionize communication systems and protect our critical infrastructure,” Disharoon said.

Disharoon was first introduced to Georgia Tech while he was getting his bachelor’s degree in electrical engineering from Kennesaw State University through a co-op he completed at the Georgia Tech Research Institute (GTRI).

Upon completing his undergraduate degree, he came to Georgia Tech where he is pursuing his ECE Ph.D., while working at the mmWave Antennas and Arrays Laboratory under the guidance of ECE Assistant Professor Nima Ghalichechian and GTRI chief scientist Joshua Kovitz.

During his time at Georgia Tech Disharoon has received support for his research from the Institute and beyond, including the ECE Freshmen Fellowship in 2021, a fellowship from Qualcomm in 2022, and the GTRI Graduate Student Fellowship in 2023.

He’s also served as a reviewer for the “IEEE Transactions on Antennas and Propagation” and the “Antennas and Wireless Propagation Letters” since 2022 and has coauthored two peer-reviewed journal articles and seven conference publications.

Jean Carlos (J.C.) Hernandez-Mejia has been named the interim director of National Electric Energy Testing, Research, & Applications Center (NEETRAC).

Hernandez-Mejia has been a research engineer at NEETRAC since 2017, contributing significantly to research, testing, and applications work in the reliability area. His work specifically focuses on condition assessment, asset management strategies, failure analysis, and optimization of power system performance. In 2022 he was promoted to senior research engineer. 

He was selected to the five-year appointment for his exceptional record of scholarship and service to the Institute.

Yu joined ECE in 2018, bringing his expertise in semiconductor devices and integrated circuits for AI hardware. He currently runs the Laboratory for Emerging Devices and Circuits.

The primary challenge in current AI acceleration is the extensive data movement cost between the compute and memory components. His research aims to close that gap to greatly improve the compute throughput and energy efficiency through innovations in a variety of memory technologies and 3D integration.

His research has received support from federal agencies like the National Science Foundation, the Defense Advanced Research Projects Agency (DARPA), Intelligence Advanced Research Projects Activity, and the Department of Education, as well as from industry sponsors such as the Semiconductor Research Corporation (SRC), Intel, the Taiwan Semiconductor Manufacturing Company, Samsung, SK Hynix, Qualcomm, Sony, IMEC, and Google.

He's received recognition and awards from some of the top organizations in his field. He was named an IEEE Fellow for his contributions to non-volatile memories and in-memory computing, and won Intel's Outstanding Researcher Award for a prototype small-scale accelerator chip that is able to quantify uncertainty in modern computer hardware, allowing for improved computing robustness.

Yu holds many other responsibilities outside of his ECE appointments for building ecosystem in the research community.

He leads the open-source NeuroSim platform that provides a benchmark tool for AI hardware that encompasses a wide range of technology flavors and supports machine learning algorithms from convolutional neural networks to transformers.

He is also the theme lead of two SRC/DARPA Joint University Microelectronics Program (JUMP) 2.0 centers on intelligent memory/storage and heterogeneous/monolithic 3D integration, as well as serving as the technical program committee for two flagship conferences in the field of semiconductors: IEEE International Electron Devices Meeting and IEEE Symposium on VLSI Technology and Circuits.

Yu also has a series of YouTube lectures that aim to train the next generation of engineers with domain expertise in memory technologies.

He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively.

Before coming to ECE he was an assistant professor at Arizona State University from 2013 to 2018.

The paper was co-authored by all undergraduate students, with guidance from ECE associate professor Vincent Mooney. Three students were from ECE: Gabrielle Calderon, Andrew Hamby, and Valeriia Rubanova. Two others were from the School of Computer Science: Olivia Blanchette and Jing Liu.

“This is the first time I have ever seen an undergraduate team take an unknown research problem with no external funding or relationship to ongoing graduate research and turn the idea into a paper which receives an award,” Mooney said.

The paper titled, “Linguistic Encryption for Underwater Communication,” examined how to use a stream cipher to encode short-fixed length sounds for a swarm of robots to communicate with each other deep under water in a cryptographically secure fashion.

The idea was to "translate" simple commands into the constructed Toki Pona language, which are then mapped to dolphin noises. The dynamic nature of the constructed language made translation and decryption very hard without the stream cipher seed, thus creating a very secure communication system.

The technology has uses in search and rescue capacities as well as general underwater topological surveying.

The paper was selected out of over 100 papers published in the conference.

All the research was done by Mooney’s Secure Hardware VIP group with no outside source of funding.

The VIP program gives undergraduate students the chance to conduct ambitious, long-term, large-scale, multidisciplinary research projects under the guidance of faculty members, giving them substantial real-world experience.

“The VIP program allowed me to explore my interdisciplinary academic interests with the depth of a full research project alongside other highly motivated students,” Calderon said. “Even before this award, the experience I gained working on this project made it extremely worthwhile, especially because we had the flexibility to pursue a somewhat unorthodox idea.”

Professor Maryam Saeedifard has been appointed a Ken Byers Professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), effective June 1, 2024.  

The award recognizes lifetime achievements by leading researchers using or facilitating neuroimaging to discover original and influential findings regarding the organization and function of the human brain.

“One of the things I really like about the Glass Brain is it symbolizes to me our desire to see beneath the surface. It's a challenge to be open and transparent in our work,” Calhoun said. “Visualization is hard and subjective, we have to work to make the links between our fancy models, the underlying data, and our conclusions about the brain, as transparent as possible.”

He's made many contributions to the field, including authorship on over 1,000 papers in industry journals, generating over 100,000 citations within the research community.

Much of his work has focused on developing data-driven approaches to study brain dynamics, multimodal neuroimaging of the brain, and brain biomarkers across a range of mental and neurological conditions.

Calhoun is the founding director of the tri-institutional Center for Translational Research in Neuroimaging and Data Science (TReNDS), a joint effort between Georgia State, Georgia Tech, and Emory University. The Center’s goal is to improve the understanding of the human brain using advanced analytic approaches with an emphasis on translational research such as the development of predictive biomarkers for mental and neurological disorders.

Calhoun received his bachelor’s degree in electrical engineering (EE) from the University of Kansas, a pair of master’s degrees in biomedical engineering and information systems from Johns Hopkins University, and a Ph.D. in EE from the University of Maryland Baltimore County.

Before coming to Georgia Tech, he worked as a research engineer in the psychiatric neuroimaging laboratory at Johns Hopkins, the director of medical image analysis at the Olin Neuropsychiatry Research Center. He’s also been an associate professor at Yale University, a distinguished professor at the University of New Mexico, and the President of the Mind Research Network.

The Glass Brain Award is the latest of many distinctions Calhoun has received during his accomplished career. He’s received fellowships from a number of organizations, including the Institute of Electrical and Electronic Engineers (IEEE), the Association for the Advancement of Science, and the American Institute of Biomedical and Medical Engineers.

He’s also won an IEEE Outstanding Engineer Award in 2014 and an IEEE Southwest Area Outstanding Educator Award in 2015.

Saligram’s paper, “Cryogenic CMOS for High Performance Computing," won third place in the conference’s Ph.D. Forum.

Cryogenic CMOS for high performance computing is a radical idea that proposes the use of ultra-low temperature devices (~77K/-196C) for server and cloud computing applications. It has gained traction due to the soaring energy costs of data center operation.

The research Rakshith presented at the conference focused on the modeling of devices and interconnects, design technology co-optimization, benchmarking and design of memory macro test chips to demonstrate the system level benefits of cryo-CMOS.

The Ph.D. Forum is a poster session hosted by the Association for Computing Machinery Special Interest Group on Design Automation and IEEE Council on Electronic Design Automation for Ph.D. students to present and discuss their dissertation research with people in the electronic design automation community.

It has become one of the premier forums for Ph.D. students in design automation to get feedback on their research and for industry to see academic work in progress. Hundreds of people attended the forums, and participation is competitive with an acceptance rate of around 30 percent.

Rakshith is a member of the Integrated Circuits and Systems Research Lab and advised by ECE Steve W. Chaddick School Chair Arijit Raychowdhury.

He will be joining the faculty of the University of Tennessee, Knoxville at the start of the Fall 2024 semester.

The prestigious award recognizes the best paper published in the TODAES, the ACM's flagship publications in the area of electronic design automation (EDA).

Yu accepted the award at the 61st Design Automation Conference in San Francisco, Calif. in June.

This is the second consecutive year Yu’s team won an award for research printed in a flagship publication in the area of EDA, and the third year in a row research from ECE has received such an honor.

The paper titled, “Hardware-aware quantization/mapping strategies for compute-in-memory accelerators,” analyzed different combinations of settings for emerging non-volatile memory (eNVM) technologies.

This new technology is important for mixed-signal Compute-in-Memory (CIM) accelerators, which are very energy efficient, thus making them crucial for artificial intelligence hardware design, which are notoriously resource intensive platforms.

Ultimately, the research found the right configuration and settings can significantly improve output and efficiency. Yu’s team was able to achieve an increase in processing speed by up to 60 percent, while doubling the energy efficiency and reducing overall hardware size by up to 25 percent.

The findings provide design guidelines to engineers who continue to research eNVM and CIM technology.

Yu co-authored the paper with ECE Ph.D. graduates Shanshi Huang and Hongwu Jiang, who are now both assistant professors in Hong Kong University of Science and Technology.

Yu’s lab won the IEEE’s Donald O. Pederson Best Paper Award in 2023 for their research on an end-to-end benchmark framework to evaluate state-of-the-art CIM accelerators. The award honors the best paper in the IEEE’s Transactions on Computer-Aided Design of Integrated Circuits and Systems, the flagship journal of the IEEE Council on Electronic Design Automation.

In 2022, ECE Professor Sung Kyu Lim and his research team won the Donald O. Pederson Best Paper Award for their paper on a physical design tool named Compact-2D that automatically builds high-density and commercial-quality monolithic three-dimensional integrated circuits.

Yu also recently received a 2023 Intel Outstanding Research Award for his work on a chip that will help quantify uncertainty that is beyond the capabilities of existing binary computing systems, and improve computing robustness.

This prestigious award recognizes top technical papers at the conference. His paper was selected out of the 306 total submissions eligible for this award this year.

His paper, “Beyond Planar: An Additively Manufactured, Origami-Inspired Shape-Changing, and RFIC-Based Phased Array for Near-Limitless Radiation Pattern Reconfigurability in 5G/mm-Wave Applications,” was co-authored by fellow ECE Ph.D. candidates Chenhao Hu and Nathan Wille, and ECE Professor Manos Tentzeris, in collaboration with George Mason University Electrical and Computer Engineering professor Kai Zeng.

Al Jamal and his team successfully demonstrated the first-ever additively manufactured, origami-inspired, shape-changing phased array at mm-wave frequencies, showcasing near-limitless reconfigurability. This work represents a significant leap, opening impactful opportunities for the advancement of massive MIMO and beyond-5G communication.

An origami-inspired, shape-changing phased array combines this traditional antenna function with the ability to electronically control the direction of the signal and mechanically change its shape through folding structures inspired by origami. This makes the antenna highly adaptable.

Al Jamal has been enrolled in the ECE Ph.D. program since 2022, and is a member of the ATHENA Lab, where he is advised by Tentzeris.

He received his bachelor’s degree in electrical and computer engineering from the American University of Beirut with high distinction.

His research interests include the use of additive manufacturing techniques in designing highly integrated, heterogeneous, and conformal/flexible RF systems encompassing RF front-end circuits, antennas, and packaging up to mm-wave frequencies. He is also keen on advocating engineering education to high school and undergraduate students.

Through his research, Al Jamal aspires to design and build communication devices and RF electronics that draw inspiration from origami and art, leading to enhanced functionality and physical flexibility to seamlessly integrate with human-centered devices, thereby enabling more efficient and integrated communication networks for digital awareness.

The award is given annually by the Office of Technology Licensing (OTL), recognizing the inventiveness of Georgia Tech's graduate students and postdocs. Winners submit projects that show commercial promise and a commitment to research and development that can contribute significantly to the betterment of society.

MicroCodes is comprised of a new microfabrication method and coding method. Initially developed as a facilitator in the characterization of Circulating Tumor Cells (CTCs), it later evolved to become a universal add-on for a number of other medical and MEMS applications.

The award acts as a direct financial investment into the future of the technology, helping to carry out different commercial processes, such as procuring materials and supplies, and carrying out customer discovery initiatives.

Valipour was one of five winners this year.

His research interests are centered around MEMS, microfabrication, bioelectronics and utilizing micro and nano engineering to understand how cancer works and how it can be managed.

He’s developed technologies and methods to characterize, monitor, and intervene in cancer to ultimately create the platform that gives an edge in the fight against cancer. To date, these efforts have resulted in seven invention disclosures to OTL, with the award-winning MicroCodes being the latest.

Valipour is currently a member of Biomedical Microsystems Laboratory. Outside of ECE, he is part of the Technology Innovation: Generating Economic Results (TI:GER) program at Scheller College of Business.

The award-winning paper, titled "TS-LSTM and temporal-inception: Exploiting spatiotemporal dynamics for activity recognition," was authored in 2019 by AlRegib and Assistant Professor Zsolt Kira in the College of Computing, as well as then-Ph.D. candidates Chih-Yao (Kevin) Ma (now a staff research scientist at Meta) and Min-Hung (Steve) Chen (now a senior research scientist at NVIDIA). the work was completed in AlRegib’s Omni Lab for Intelligent Visual Engineering and Science (OLIVES).

The research explores different methods to improve action recognition in videos using deep neural networks, specifically two-stream Convolutional Neural Networks (ConvNets). It investigates how to better capture the spatiotemporal dynamics within video sequences. The study proposes and evaluates two new network architectures: temporal segment RNN and Inception-style Temporal-ConvNet. These architectures aim to effectively integrate spatiotemporal information and enhance the overall performance of action recognition systems. The research also identifies specific limitations of each method, which could guide future work in this area.

The EURASIP Best Paper Award is bestowed upon exceptional papers published in journals sponsored by EURASIP within the past four years. This ensures that the most influential and vital ideas in the field are honored.

The Georgia Tech team will be honored at the European Signal Processing Conference (EUSIPCO) held in Helsinki, Finland, from September 4-8. EUSIPCO offers a comprehensive technical program addressing the latest developments in signal processing research and technology, along with its diverse applications.

EURASIP, founded in 1978, has been a crucial platform for researchers, providing an academic and professional forum to disseminate and discuss all aspects of signal processing, fostering growth and collaboration within the community.
 

Caption for photo header: Overview of the proposed framework. Spatial and temporal features were extracted from a two-stream ConvNet using ResNet-101 pre-trained on ImageNet, and fine-tuned for single-frame activity prediction. Spatial and temporal features are concatenated and temporally-constructed into feature matrices. The constructed feature matrices are then used as input to both of our proposed methods: Temporal Segment LSTM (TS-LSTM) and Temporal-Inception.

She won the award for her research, "Interface Engineering for High-Performance Memories at Elevated Temperatures," which aims to improve memory robustness at high temperatures.

Emerging memories are essential for AI applications due to their substantial memory demands. These memories must function reliably at elevated temperatures, such as high bandwidth memory operating at 105 degrees C, monolithic back end at 125 degrees C, and automotive applications at 160 degrees C.

Ensuring robustness at these high temperatures is crucial for maintaining performance and reliability.

At the event, Afroze demonstrated an interface engineering method to enhance the robustness of these memories at elevated temperatures, ensuring their effectiveness under realistic temperature conditions.

“Attending the JUMP 2.0 SUPREME annual meeting in Cambridge was truly remarkable,” Afroze said. “Engaging with top semiconductor researchers from both academia and industry was incredibly inspiring. I'm grateful for the insights and connections gained, shaping my vision for future advancements in technology.”

The SUPREME center, led by Cornell University, is one of the seven Joint University Microelectronics Program (JUMP) 2.0 academic research centers co-sponsored by Semiconductor Research Corporation’s (SRC).

It aims to demonstrate the basic materials and technology breakthroughs needed to address the seismic shifts identified by the semiconductor community in the Decadal Plan for Semiconductors.

Afroze is a third-year Ph.D. candidate under the supervision of ECE associate professor Asif Islam Khan, who is part of the SUPREME Center team.

Her research interests encompass a comprehensive study of ferroelectric memories, from microstructure analysis to electrical characterization, aiming to advance the understanding and application of the ferroelectric materials in next-generation memory technologies.

The paper introduces an innovative design for a high-density, power-efficient 3T embedded dynamic random-access memory (eDRAM) with the back-end-of-line (BEOL) compatible tungsten-doped indium oxide (IWO) channel transistor. This novel architecture incorporates both near-memory computing (NMC) and in-memory computing (IMC) capabilities within a single array.

The proposed 3T IWO eDRAM offers remarkable advantages, including significantly reducing the area needed for in-memory computing. This is achieved through condensed design and leveraging monolithic 3D integration.

IWO channel transistors also substantially improve data retention compared to traditional solutions due to low sub-threshold leakage, making it an excellent candidate for last-level cache and parallel computing in next-generation computing systems. This will allow for a reduction in energy consumption, while performing data-intensive processes, such as artificial intelligence (AI) computing.

The research is supported by the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES) and Center for Processing with Intelligent Storage and Memory (PRISM), operating under the Semiconductor Research Corporation (SRC)'s Joint University Microelectronics Program 2.0 (JUMP 2.0), in collaboration with the Defense Advanced Research Projects Agency (DARPA). 

The grant is awarded to 10 Ph.D. candidates, facilitating the mobility for them to conduct interdisciplinary research at another research department. The recognition of Kwak’s research also further acknowledges the potential of monolithic 3D integration to extend Moore's Law and address the ever-increasing computational demands of emerging technologies like AI.

Kwak is a member of ECE Professor Shimeng Yu's Laboratory for Emerging Devices and Circuits.

The research group's primary focus is to overcome the limitations of conventional 2D scaling in integrated circuits by vertically stacking circuit components using emerging devices in 3D monolithic integration.

In this role, Professor Davenport will serve as the School’s primary representative on all matters related to graduate academics. He will oversee the graduate affairs team, lead the graduate admission process, develop programs and assessments, and collaborate closely with the chair and associate chairs on academic initiatives.

"We are thrilled to have Mark step into this vital role,” said Arijit Raychowdhury, Steve W. Chaddick School Chair and professor. “His extensive experience and forward-thinking approach will be invaluable as we continue to attract top Ph.D. talent. I am confident that his innovative ideas and collaborative approach will significantly enhance our graduate programs."

Georgia Tech's ECE graduate program is among the largest in the country, with over 1,300 students. It holds a top-five national ranking, including No. 2 among public universities, per U.S. News & World Report.

Since 2018, Davenport has served as the graduate recruitment coordinator for ECE, where he played a strategic role in working with the ECE Graduate Affairs Office and the School’s Graduate Student Recruitment Committee to recruit top Ph.D. candidates and improve the matriculation rate of exceptional applicants.

Joining the ECE faculty in 2012, Davenport’s previous roles include serving as an NSF Mathematical Sciences Postdoctoral Research Fellow at Stanford University and a visitor with the Laboratoire Jacques-Louis Lions at the Université Pierre et Marie Curie. He holds a B.S.E.E., M.S., and Ph.D. from Rice University.

His research focuses on the role of low-dimensional models and optimization in signal processing, statistical inference, and machine learning. He has received several prestigious awards, including the NSF CAREER Award, the Air Force Office of Scientific Research Young Investigator Award, the Sloan Research Fellowship, and the Presidential Early Career Award for Scientists and Engineers (PECASE). Additionally, he currently serves as a Senior Editor for IEEE Transactions on Signal Processing and is a two-time winner of the fastest faculty member award in the Pi Mile Road Race.

Davenport succeeds Mathieu Bloch, who was named Associate Dean of Academic Affairs in the College of Engineering in January.

The research, done in collaboration with Emory University and Johns Hopkins University, focuses on new device technologies to support innovation in optogenetics, a technique used to control neuron activity or other cell types with light.

The two-day conference, hosted by Rice University and the Texas Medical Center, connects researchers, clinicians, and business leaders in the fields of neuroengineering, neurotechnology, neuroscience, and neurosurgery.

The award recognizes excellence in oral presentation among presented posters. There were 70 total posters accepted to this year’s conference.

Lu and fellow researchers in ECE Professor Muhannad Bakir’s Integrated 3D System Group are working on integrating a μLED chip with a flexible microelectrode array (MEA) for optogenetic activation, while simultaneously recording electrical activity in muscle tissue.

Recently, they developed an MEA with a single blue LED, which allows for targeted activation of specific opsins. Opsins are light-sensitive proteins that can be expressed in specific cells to control their activity using light.

So far, the technology has been successful in activating facial muscles and inducing jaw movement in transgenic mice.

“I had a rewarding time at the InterfaceRice conference,” Lu said. “The feedback on my project was highly encouraging, and discussions extended beyond engineers to include clinicians - actual users of my technology - who offered invaluable insights. These conversations also led to several opportunities for potential collaborations, which was very exciting.”

The next step in the research for Lu and her collaborators is to add multiple optical channels and incorporate more LED colors, allowing them to activate and observe more opsins.

TCPMT is the flagship journal of the IEEE Electronics Packaging Society (EPS).

He was recognized for the paper he co-authored prior to his graduation, “Benchmarking and Demonstration of Low-Loss Fused-Silica Stitch-Chips with Compressible Microinterconnects for RF/mm-Wave Chiplet-Based Modules.”

It proposes and benchmarks ‘fused-silica stitch-chips’  as an interconnect technology between neighboring RF/mm-wave chiplets. Compared to conventional advanced packaging technologies, the stitch-chips enable low-loss and broadband interconnection, provide built-in mechanical deformation capability to compensate for differing chiplets heights, and provide a path towards package size scaling for large-scale multichiplet integration.

He was advised by ECE Professor and 3D Systems Packaging Research Center Director Muhannad Bakir.

Zheng is the second student from Bakir’s Integrated 3D Systems Lab to have their research recognized. Shengtao Yu won the Intel Outstanding Student Paper Award for this paper on co-packaged optics and fiber-chiplet-connectors at the 2023 IEEE Electronic Components and Technology Conference (ECTC), which is the flagship conference of IEEE EPS.

It is a rare honor for the same research group to win paper awards in the same year from both ECTC and TCPMT.

At the end of May, Zheng, Yu and Bakir will all attend ECTC 2024 in Denver, CO to receive the ECTC and TCPMT paper awards. 
 

The award, which is named after Georgia Tech’s first full-tenured female engineering professor, is given annually to one female-identifying student who excels in their academic pursuits and also works to create a more inclusive and diverse engineering community.

Wolfe was nominated by the School of Electrical and Computer Engineering (ECE) for her passionate efforts in encouraging women to pursue engineering degrees and careers. 

She’s heavily involved in all three Georgia Tech women in engineering organizations: Society of Women Engineers, Women in Engineering, Women in Electrical and Computer Engineering, participating as a mentee as well as a mentor.

She’s also a peer leader in ECE 1100, and a respected teaching assistant in ECE 2035.

As a transfer student herself, the importance of finding community is something Wolfe knows very well. Her impact on other students has been significant, with many peers saying she’s helped foster a sense of belonging not just in ECE but across the entire Institute. 

Her passion also comes through in her many research projects. Wolfe was a research assistant for ECE Associate Professor Linda Wills and Professor of the Practice Tom Collins' “Relatable Rebound Story.” The project, which won a grant from Transformative Teaching and Learning (TTL), collects stories of overcoming adversity from students in ECE 3025 and shares them with future students to help encourage completion of the notoriously difficult class.

On top her Georgia Tech responsibilities, she’s also held a software internship at Apple and completed three co-op rotations at NASA’s Marshall Space Flight Center. 

After graduating this spring, Wolfe will be taking her talents to AT&T as a network engineer through their Technical Development Program. She also plans to pursue an online master’s in computer science through Georgia Tech.

And they couldn’t be more excited.

“This is huge,” Deanna Yancey said. “I probably will cry. I don’t usually cry in front of people, but I probably will get a little teary.”

Choosing Her Path

She began building computers with her father when she was growing up in Columbia, Maryland, and eventually realized she wanted to learn more about the electrical side of things. Yancey applied to, and was accepted at, Georgia Tech but chose to pursue electrical engineering at Penn State instead.

“I think my family was surprised by that decision but still extremely happy for me,” she said. After graduating, she began a three-year rotational program at Northrop Grumman in Maryland, which she will complete in August.

She also applied to Tech again, this time for an online master’s in electrical and computer engineering. “I didn’t tell my family I was applying, so when I got in, I got to read the acceptance email to my grandfather,” Yancey recalled. “He was so happy. He almost started jumping; he was so excited.”

With good reason.

‘That Is Inspiring’

Despite the hardships her grandfather experienced, he speaks highly of Georgia Tech. “That is inspiring to me,” she said. “Even though it was hard, you still recognize the institution for being top-notch and having some of the best engineers coming out of there. And, Tech has significantly changed — he’s very happy to have seen the changes.”

When she was younger, her grandfather didn’t display much Georgia Tech memorabilia around the house and rarely spoke about his time there. As a Black student at an otherwise all-white university in the early 1960s, Ronald Yancey faced the ugliness of backlash and hostility every day.

“Even now, he’ll talk about some of the things he went through, but he won’t tell us everything because he knows it would be upsetting to our family.”

Takeaways From Tech

Summing up her graduate school experience, Yancey said she appreciated “getting the same education as everybody else. They don’t treat the online students differently from the in-person students.” She was also excited that all her professors had industry experience and a passion for what they do. “I think it’s truly amazing to get that firsthand experience.”

Yancey couldn’t attend the 2019 unveiling of the First Graduate sculpture of her grandfather in the Clough Undergraduate Learning Commons, but whenever she visits campus, she takes friends to see it.

While she is figuring out her next role at Northrop Grumman, she wants to pursue a career in management to help the next generation of young engineers.

Passing the Baton

“We are extremely proud that Deanna took the initiative to select her field, to quietly and quickly apply, arrange her curriculum, and follow through with the completion of her matriculation,” Ronald Yancey said. “Deanna's graduate degree is truly an impressive achievement."

From a granddaughter’s perspective, “It signifies the passing of a baton from one engineer to another. But more importantly, the struggle that he saw is not the struggle that’s going on now.”

Inan was named a Regents’ Entrepreneur, the highest distinction from the system and recognizes faculty members for academic, innovation, and entrepreneurial excellence.

The designation is bestowed upon the unanimous recommendation of the USG institution president, the chief academic officer, and the chancellor, and upon the approval of the Committee on Academic Affairs.

“Omer is exceedingly deserving of this appointment, and we are so proud of everything he’s accomplished with ECE,” Steve W. Chaddick School Chair and Professor Arijit Raychowdhury said. “We pride ourselves on fostering an entrepreneurial environment at ECE and Omer has been an integral part of that.”

Inan’s research focuses on developing new technologies to monitor and quantify human health, including allowing patients with chronic diseases to track their health at home. He is working to design systems that help patients measure cardiac data to track their heart health. Other technologies would noninvasively quantify stress and modulate the body’s response to help treat post-traumatic stress disorder (PTSD) and listen to joints to assess musculoskeletal health.

In recent years, the U.S. Food and Drug Administration has designated two technologies developed based on Inan’s research as Breakthrough Devices, accelerating their use for patients. One is a handheld noninvasive vagus nerve stimulation device (from electroCore, Inc.) to reduce the physiological response to stress for PTSD patients. The other is an algorithm and wearable device to monitor patients with heart failure. The algorithm and wearable device are part of a company Inan cofounded called Cardiosense.

Inan is a fellow of IEEE, the American College of Cardiology, and the American Institute for Medical and Biological Engineering.

This is the third year in a row an ECE faculty member has received the honor. Inan joins Jennifer Hasler, Raghupathy Sivakumar, and Farrokh Ayazi as ECE recipients of the Regents’ Entrepreneurs title.

Overall, 19 Georgia Tech faculty members were honored with 2024 Regents' Distinctions.

She was recently notified of the award for her presentation, “Describing the Analog Resistance Change of HfOx Neuromorphic Synapses,” given at the Materials Research Society’s (MRS) Fall 2023 Meeting in Boston.

The research was recognized for its contributions to future materials and technologies toward sustainable heterogeneous computing and energy-efficient machine learning.

MRS brings together materials researchers from around the world to promote the sharing and communication of interdisciplinary research and technology to improve the quality of life.

Athena, an IBM Ph.D. Fellow, conducted the research with her advisor, Eric M. Vogel, a Hightower Professor in the School of Materials Science and Engineering (MSE), with an adjunct appointment in School of Electrical and Computer Engineering (ECE).

She presented a compact model, Compact Series Trap-Assisted Tunneling and Ohmic conduction (C-STAO), which enables the rapid simulation of artificial HfOx synaptic devices. The model provides deep insights into the analog temporal responses and temperature dependency of artificial synaptic devices, which are used to develop brain-inspired circuits.

These brain-inspired circuits are important for the development of AI systems and can help them to meet increasing computational demands while achieving more human-like cognitive capabilities with improved efficiency.

It also furthers Athena’s Ph.D. research, dedicated to the development of adaptive oxide devices for neuromorphic computing, aimed at replicating the human brain's functionality for more intelligent and energy-efficient computing.

Funding Acknowledgement

This project was supported by the Air Force Office of Scientific Research MURI entitled, “Cross-disciplinary Electronic-ionic Research Enabling Biologically Realistic Autonomous Learning (CEREBRAL)” under Award No. FA9550-18-1-0024.

This work was performed in part at the Georgia Tech Institute for Electronics and Nanotechnology, a member of the National Nanotechnology Coordinated Infrastructure (NNCI), which is supported by the National Science Foundation (No. ECCS-1542174). The work was also supported by the Cadence Diversity in Technology Scholarship and the IBM Ph.D. Fellowship Award No. 2022-2024.

The award recognizes exceptional contributions made through Intel university-sponsored research that aligns with Intel’s mission of creating world-changing technology to improve daily life.

He was recognized for his project “Simulation of Probabilistic Learning Ecosystems (SIMPLE),” with Ian Young and his team at Intel's Components Research Labs.

While most modern computer hardware is primarily based upon determinist zeros and ones, there are some phenomena that create uncertainty that is beyond the capabilities of this binary system.

Yu’s team used conventional and emerging technologies and novel hardware-software co-design for pathfinding of a prototype small-scale accelerator chip. This super energy-efficient probabilistic hardware will be able to quantify this uncertainty and compute with more robustness.

The team now looks to further research and prototype the design into silicon.

Through this industry-academia collaboration, multiple students from Yu’s Laboratory for Emerging Devices and Circuits have interned at Intel and been hired by the company for full-time positions.

He is the first Georgia Tech faculty to receive the honor since Saibal Mukhopadhyay in 2019. More recently, ECE assistant professor Cong (Callie) Hao won an Intel Rising Star Faculty Award in 2023.

Yu’s work has been recognized with a number of recent awards, including the Semiconductor Research Corporation (SRC) Inaugural Young Faculty Award in 2019 and the ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award 2020. He was named an Institute of Electrical and Electronics Engineers (IEEE) Fellow in 2023.

Among the select group of researchers involved in a specific project are professors Cong “Callie” Hao and Pan Li in the Georgia Tech School of Electrical and Computer Engineering (ECE). 

Hao and Li will play a pivotal role in the "Intelligent Experiments Through Real-time AI: Fast Data Processing and Autonomous Detector Control for sPHENIX and Future EIC detectors" project; a $2 million endeavor being led by Ming Xiong Liu of the Los Alamos National Laboratory (LANL).

“I am thrilled to see how our achievements in computer architecture research can have cross-disciplinary impact on high-energy physics experiments, extending well beyond mere academic papers and hardware prototypes,” said Hao. “We are highly motivated and proud to tackle real-world problems by offering solutions that are both intelligent and practical.”

Hao and her research team will work to furnish an ultra-fast field programmable gate arrays (FPGA) system for particle detection and tracking in high-energy physics experiments. The system will be equipped with an automated design flow that eliminates the need for manual intervention. Achieving this necessitates sophisticated hardware optimizations, coupled with algorithmic innovations, according to Hao.

Li and his team will contribute to the development of robust learning algorithms via domain adaptation methods, aiming to address the online shift of the beam point of particle collisions.

All projects are supported by the DOE Office of Science, Nuclear Physics Program, and were selected through a rigorous and competitive peer review process. According to the DOE press release, the fifteen projects will be conducted by researchers at eight DOE national laboratories and 22 universities. Projects will include the development of deep learning algorithms to identify a unique signal for studying physics of fundamental symmetry in extremely rare nuclear decays that if observed would demonstrate how our universe could have become dominated by matter rather than antimatter.

The work centers on wearable joint health monitoring through acoustical sensing. It presents a miniaturized, fully digital sensing system designed for convenient attachment to the knee using adhesive. The system offers potential applications in streamlined data collection for monitoring athletes and individuals with joint disorders, as well as future prospects for decentralized digital clinical trials.

The paper was first authored by Ph.D. candidate Mohammad Nikbakht and senior authored by Inan.

“The KneeMS system that Mohammad has built is a noteworthy step forward in wearable health monitoring,” said Inan. “It not only signifies progress in monitoring joint health but also hints at potential shifts in how we conduct clinical trials and approach treatments and therapies.”

Nikbakht and Inan were presented the award at IEEE BSN 2023 on October 9 in Cambridge, Mass. IEEE BSN unites academia, industry, healthcare, and non-profit leaders and experts, offering a cross-disciplinary single-track forum for pioneering research on devices and sensors, as well as hardware and software system.

Top photo caption: Professor Omer Inan (left) and Ph.D. candidate Mohammad Nikbakht with the IEEE BSN 2023 Best Paper award.

The initiative provides scholarships and real-world experience to undergraduates who are interested in power and energy engineering careers. Dimitrova was one of 82 undergraduate students to receive the honor this year.

She was inspired to apply for the scholarship by School of Electrical and Computer Engineering (ECE) research engineer Zhiyang Jin during her Fall 2023 ECE 3072 class.

“I recommend all students going into power to apply for this program,” Dimitrova said. “I think it's a great initiative to continue inspiring and highlighting a path for students in this field where we will have to meet the increasing energy demands of the future.”

Dimitrova plans on using the scholarship to continue her studies and research, focusing on electric energy systems and circuit technology threads.

She’s conducted research in ECE Professor Deepakraj Divan’s Center for Distributed Energy, focusing on modular battery storage systems for energy access in emerging markets.

Outside of the classroom, she’s had several internships in power generation and storage, is an ECE Ambassador, a Benchtop MPI volunteer at the Hive Makerspace, and a sea kayaking staff member for Outdoor Recreation Georgia Tech (ORGT).

These experiences have had a profound effect on her academic journey and career development, as a recent expedition to Antarctica with ORGT inspired her to shift the applications of her research to assist in the maintenance of the extreme environments on Earth and aid in creating a more sustainable industry.

The 2024 PES Scholar application opens in March.

With climate change becoming one of the a defining issue of the 21st century, the transition to a low-carbon energy system will solve about three-fourths of the problem, according to the fellowship’s website. At the same time, the new energy system needs to be affordable, reliable, and available to the average person.

The three-year fellowship sponsored in Stanford’s Precourt Institute of Energy and Doerr School of Sustainability aims to identify, develop, and connect the next generation of energy leaders — from science and engineering to policy and economics — to translate theoretical climate change solutions into tangible realities.

At Stanford, Athena, who is advised by Eric M. Vogel in the School of Materials Science and Engineering, will work on emerging materials and devices for energy-efficient sustainable computing. She will be working with H.-S. Philip Wong, professor of electrical engineering, and Alberto Salleo, professor of materials science and engineering.

After being selected as a finalist, she presented her current Ph.D. research on adaptive oxide devices for energy-efficient computing, as well as her proposed research to the fellowship’s advisory board.

“It was an amazing experience to go through the selection process of writing the proposal and finally getting interviewed by the honorable advisory board,” Athena said. “It was humbling to get the opportunity to discuss my research with a person I have always looked up to in Professor Steven Chu, a Nobel Laureate in Physics and former U.S. Secretary of Energy!”

Athena is just one of 10 fellows selected globally this year. The fellowship provides her the opportunity to explore new and profound postdoctoral research that is distinct from her Ph.D. work.

“I am deeply grateful to my advisor Prof. Eric M. Vogel for his constant kind support throughout my Ph.D. and for believing in me,” Athena said. “He has been a pillar of constant support throughout my journey. I am also grateful to Prof. Samuel Graham for his kind constant support, including for this fellowship. I am thankful to my respected P.I.s at Stanford, Professor H.-S. Philip Wong, and Professor Alberto Salleo for their support of my proposal. I am also grateful to my respected mentors Prof. Suman Datta, Prof. William Alan Doolittle, Dr. Takashi Ando, and Dr. Vijay Narayanan for their kind support, advice, and opportunities. Finally, I would like to thank Georgia Tech ECE for providing the platform for learning, exploration, and collaboration.”

Before her time at Georgia Tech, Athena received her undergraduate degree in materials science and engineering from the Bangladesh University of Engineering and Technology. She then spent two semesters at Purdue University as a graduate researcher, where she collaborated with the Idaho National Lab on nuclear materials for next-generation energy.

Athena’s research has been recognized with the Georgia Tech ECE Ph.D. Fellowship, 2022 Cadence Diversity in Technology Scholarship, 2023 EECS Rising Stars, 2023 Colonel Oscar P. Cleaver Award for the most outstanding Ph.D. dissertation proposal in Georgia Tech ECE, 2023 MRS Graduate Student Award, and IBM Ph.D. Fellowship from 2022-2024.

He presented his paper, “Scalable Fiber-Array-to-Chip Interconnections with Sub-Micron Alignment Accuracy,” at the conference in June 2023 and was recently notified of the outstanding paper recognition.

The paper explored co-packaged optics (CPO) for next generation AI and mm-wave electronic systems, which will require optical connectivity in very close proximity to the electronics.

“I got valuable technical feedback from the audience,” said Yu, a Ph.D. candidate in the School of Electrical and Computer Engineering. “I also learned more about the exciting trends in the packaging industry.”

His co-authors were his Ph.D. advisor Muhannad Bakir and co-advisor ECE Regents Professor Thomas Gaylord. Bakir also serves as the Interim Director of the GT 3D Systems Packaging Research Center (PRC).

The research presented innovative design and technology to enable the passive alignment and interconnection of an array of optical fibers to an underlying photonic integrated circuit (PIC). The key to the demonstrated technology is a passive silicon chiplet, which contains 3D printed slots for fiber insertion, that precisely self-aligns to an underlying PIC at sub-micron scale.

This has the potential to eliminate active alignment techniques commonly used in photonics packaging and enable a scalable and silicon-based solution to fiber alignment and coupling. Photonic interconnection between modern 2.5D packages with PICs and optical fibers is a current key bottleneck.

This work will potentially lead to improved and scalable CPO architectures, enabling massive off-package bandwidth and reduced energy consumption of interconnects in data centers, which will be important to meet the rapidly increasing packaging demands of artificial intelligence applications and beyond.

The work was supported by the United States Air Force under Contract FA8650-20-C-1003 and in part by the Georgia Tech Institute for Coordinated Infrastructure (NNCI), through the National Science Foundation under Grant ECCS-2025462.

Yu plans to continue this research in Bakir’s Integrated 3D Systems Group to create more robust and scalable designs that are compatible with the latest semiconductor technology.

Marshall, who is pursuing her M.S. and Ph.D. in ECE, received the award for her talk "Pushing the Limits of Low-Temperature Growth of Improved-Quality ScAlN Via Metal-Rich Epitaxy,” and Matthews, a recent ECE Ph.D. graduate, for his talk “Surface Oxide Removal on AlN Substrates via Low Temperature Aluminum Flashing.” 

The conference featured over 1,200 participants and 400 presentations. Marshall and Matthews were among just a handful of students to have their research recognized. 

Marshall’s talk presented her team’s prior success with growing improved-quality scandium aluminium nitride (ScAlN) and observations of a ScAIN coverage dependent and substrate temperature dependent scandium (Sc) catalytic effect. It also emphasized the importance of Marshall’s current research in quantifying the Sc catalytic effect to improve ScAlN films and devices. 

They both conducted their research in Professor Alan Doolittle’s Advanced Semiconductor Technology Facility. The main focus of the lab is the advancement of semiconductor technology. 

Their current research utilizes molecular beam epitaxy (MBE) to grow films, uniquely using metal modulated epitaxy (MME), a specialized technique of MBE developed by the group that helps them to precisely control the buildup of metal film on the surface of the samples. This process creates higher-quality films at low temperatures. 

The International Telecommunication Union (ITU) predicts global mobile video traffic will account for more than 75 percent of total mobile traffic by 2030 due to the rise in virtual reality, augmented reality, and high-fidelity mobile holograms.

Conventional low-efficient on-chip antenna arrays are unlikely to be able to efficiently transmit these next-generation data-intensive applications.

Lee’s project aims to design and create a 60 GHz electronically scanned array for high-speed wireless systems to help handle the potential huge increases in throughput.

He has conducted the research thus far in the mmWave Antennas and Arrays Laboratory under the supervision of ECE Assistant Professor Nima Ghalichechian.

The grant, which awards $5,000 to 10 Ph.D. candidates globally each year, aims to encourage careers in advanced electromagnetics, with selection based on the creativity and quality of proposed projects, along with discussions on the student's technical interests and skills.

Lee received his B.S. in computer and communication engineering from Korea University, and his M.S. in electrical engineering from the Pohang University of Science and Technology (POSTECH).

Prior to his time at Georgia Tech, he worked at Samsung Research and SK Hynix.

He’s published 4 peer-reviewed journal articles, 11 international conference papers, and is the inventor of 19 patents.

His research interests include mmWave on-chip antennas, phase-change material reconfigurable RF devices, and robotic antenna measurement techniques, which has won him a number of awards such as the 2023 CREATION Award from Georgia Tech and the 2018 Best Paper Student Award from the IEEE International Symposium on Antennas and Propagation.

The award-winning poster, titled “Towards Bit Error Robust Energy-Efficient Autonomous Systems”, presents a cross-layer robust learning framework aimed at achieving aggressive energy-saving yet computational-resilient autonomous swarms.

The research tackles the challenges of the distributed resource-constrained nodes, complex cyber-physical autonomous systems and increased chip bit failures, by proposing innovative approaches including robust offline/on-device learning, collaborative swarm optimizations, and dynamic thermal-payload adjustments.

Applied across hardware chips, swarm systems, and various autonomous scenarios, the technique demonstrates consistent performance-efficiency-robustness improvements for multi-drone systems.

This acclaimed research is a product of a collaborative effort between Georgia Tech, IBM Research, Harvard University, and Lawrence Livermore National Laboratory (LLNL). The work is supported in part by the Center for the Co-Design of Cognitive Systems (CoCoSys), the IAPRA MicroE4AI program, and the Center for Research into Novel Compute Hierarchies (CRNCH) PhD Fellowship.

Zishen is advised by ECE professors Arijit Raychowdhury and Tushar Krishna. His research interests center around computer architecture, VLSI, and embedded systems, with a focus on building hardware and systems for cognitive intelligence and autonomous machines, aiming to advance their performance, efficiency, resilience, and trustworthiness.

She won the award for her research on emerging materials and devices that promote energy-efficient computing. MRS brings together materials researchers from around the world to promote the sharing and communication of interdisciplinary research and technology to improve the quality of life.

She is advised by Eric M. Vogel, Ph.D., ECE adjunct professor and Hightower Professor in the School of Materials Science & Engineering (MSE).

Athena, who is also an IBM Ph.D. Fellow, presented her award-winning research at the meeting, and gave talks about two of her other research projects, “A Novel Electrical Bias Technique to Recover Degraded ReRAM Arrays for Deep Learning” and “Describing the Analog Resistance Change of HfOx Neuromorphic Synapses.”

She was also one of five global finalists for the Arthur Nowick Graduate Student Award for teaching and mentoring.

This is the latest in a growing list of honors for Athena. She’s also been recognized with the ECE Ph.D. Fellowship, Cadence Diversity in Technology Scholarship, EECS Rising Stars 2023, and Colonel Oscar P. Cleaver Award for the most outstanding Ph.D. dissertation proposal in ECE.

Before her time at Georgia Tech, Athena received her undergraduate degree in Materials Science and Engineering from the Bangladesh University of Engineering and Technology. She then spent two semesters at Purdue University as a graduate researcher, where she collaborated with Idaho National Lab on nuclear materials for next-generation energy.

Since coming to Georgia Tech, she’s received her M.S. in ECE and has been active in Women in Electrical and Computer Engineering (WECE) and Women in Material Science and Engineering (WiMSE), helping to increase the involvement of women and minorities in STEM.

Juang is the Motorola Foundation Chair Professor in the Georgia Tech School of Electrical and Computer Engineering and a Georgia Research Alliance Eminent Scholar. Co-authors of the paper are Professor Geoffrey Ye Li, research associate Zhijin Qin, and Ph.D. candidate Huiqiang Xie, all associated with Li’s Intelligent Transmission and Processing Laboratory at Imperial College London.

Leveraging recent strides in deep learning and natural language processing, the paper, “Deep Learning Enabled Semantic Communication Systems,” seeks to redefine communication systems at the semantic level. The research proposes DeepSC, a deep learning-based semantic communication system designed for text transmission. Built upon the Transformer architecture, DeepSC aims to enhance system capacity and minimize semantic errors by focusing on recovering sentence meaning, as opposed to the bit- or symbol-errors seen in traditional communication methods.

Additionally, transfer learning is introduced, to ensure adaptability across diverse communication environments and expedite model training. A novel metric called sentence similarity is also initiated to accurately assess the performance of semantic communications.

In comparison to traditional communication systems that overlook semantic information exchange, DeepSC proves to be more resilient to channel variations and demonstrates superior performance, particularly in low signal-to-noise (SNR) scenarios, as evidenced by extensive simulation results.

The award-winning paper was originally published in IEEE Transactions on Signal Processing, Volume 69, in 2021. Eligibility for the IEEE SPS Best Paper Award is based on a six-year window and honors the authors of a paper of exceptional merit dealing with a subject related to the Society’s technical scope, and appearing in one of the Society’s solely owned transactions.

The team will be honored at the 2024 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2024) in Seoul, Korea this April.

The prestigious award recognizes individuals for their, “outstanding contributions to the technology associated with the generation, transmission, distribution, application, and utilization of electric power for the betterment of society.”

Divan, holding the John E Pippin Chair and serving as a Georgia Research Alliance Eminent Scholar in the Georgia Tech School of Electrical and Computer Engineering, is being honored for his significant contributions to advanced power conversion technologies for the modern electric power grid. He will be celebrated during the IEEE Vision, Innovation, and Challenges Summit and Honors Ceremony in Boston on May 3, 2024.

With over 40 years of experience in academia and industry, Divan is a globally recognized authority in power electronics, power systems, smart grids, and distributed control of power systems. He is currently the director of the Center for Distributed Energy at Georgia Tech, leading advanced research and technology development aimed at transforming electricity delivery and utilization.

His extensive portfolio includes over 85 issued and pending patents, as well as 400 refereed publications. Through his research and entrepreneurial endeavors, he has played a pivotal role in advancing power grid monitoring, analytics, and optimization.

He is a member of the of the U.S. National Academy of Engineering, the National Academies Board on Energy and Environmental Systems, and the National Academies (NASEM) Committee on the Future of Electric Power in the United States. Additionally, Divan is a Fellow of IEEE and has previously served as the president of the IEEE Power Electronics Society. He has been honored with the IEEE William E Newell Field Medal and IEEE Hingorani Custom Power Medal.

As the International Chair of the IEEE Empower a Billion Lives (EBL) recurring global competition, Divian actively contributed to the development of scalable energy access solutions. His expertise was recognized at the White House Electrification Summit in 2022, and he has shared insights on electric grids worldwide, with notable appearances including the 2016 Conference of the Parties of the United Nations Framework Convention on Climate Change Conference (or COP 22) meeting in Morocco and the United Nations Global Solutions Summit in 2023.

Divan is an established entrepreneur, having started several companies, including Varentec, which was funded by leading green-tech Venture Capital firm Khosla Ventures and renowned investor Bill Gates. He has founded or seeded several other new ventures including GridBlock, GigaGrid, Soft Switching Technologies, Innovolt, and Smart Wires, which together have raised >$500M in venture funding.

He is the first member of the Georgia Tech faculty to be honored with the IEEE Medal in Power Engineering, an accolade that has been presented since 2010.

At the forefront of this evolving data storage landscape, a collaboration between the Georgia Institute of Technology and Samsung seeks to substantially decrease the voltage in existing technology, unlocking the full potential of AI systems.

“Finding innovative solutions in data storage is paramount, it’s not just about saving photos or documents anymore. The storage needed is about enabling AI systems to transform how we interact with our devices, the world around us, and even each other,” said Asif Khan, an assistant professor in the School of Electrical and Computer Engineering (ECE) with a joint appointment in the School of Materials Science and Engineering (MSE).

Khan's lab is spearheading the collaboration which brings together three ECE labs, including those of Professors Suman Datta and Shimeng Yu. The lead author of the paper is Dipjyoti Das, a postdoctoral fellow under Khan's supervision. The second author, Hyeonwoo Park, conducts research under Datta. The team is joined by researchers from MSE, the Institute of Materials, the Institute of Electronics and Nanotechnology, and a dedicated team from Samsung.

“This is a pivotal era of transformation and opportunity in high-memory compute,” said co-author Suhwan Lim, an engineer at Samsung. “Strategic intersectoral relationships like this between Samsung and Georgia Tech nurture innovative thinking and lead to exciting experiential results that push us all forward.”

Adding to the already substantial Georgia Tech presence in the field of computer memory storage, the team's findings will be featured at the upcoming International Electron Devices Meeting (IEDM) in San Francisco this month.

The Quest for Voltage Efficiency

The research focuses on improving NAND flash technology found at the core of storage devices like solid-state hard drives, USB sticks, and SD cards. NAND boasts an impressive 1,000-layer 3D architecture, cramming 100 terabytes of data into a minuscule space.

However, the critical challenge is NAND’s persistent high voltage requirements. Exceeding 20 volts poses challenges in computing due to increased energy consumption, heat generation, and the risk of damaging electronic components.

“NAND has been the backbone of data storage, so our research doesn't attempt to replace it; it's an upgrade. We're boosting NAND's power and pushing it into the digital storage future,” said Das, who designed and executed experiments, as well as contributed to characterization.

A Ferroelectric Future

The paper’s groundbreaking proposal aims to revolutionize NAND flash technology by replacing the traditional NAND gate stack — a multi-layered structure in a transistor essential for controlling the flow of electrical current in semiconductor devices — with a new ferroelectric structure and a tunneling barrier.

The team's method, introducing aluminum oxide (Al2O3) in the middle of the ferroelectric stack, has dramatically improved data storage capability, reducing voltage requirements by an impressive 40-60%.

Additionally, the study reveals that the Al2O3 layer functions as a tunnel barrier, impeding electron motion and establishing a dipole, creating an additional electric field that aligns with the polarization direction, boosting device memory performance.

The experiential findings could transform various sectors, including AI, mobile devices, edge data processing, embedded systems, and overall computing efficiency. 

“This breakthrough charts a new course towards more efficient, reliable and dense data storage solution,” said Datta, who is the Joseph M. Pettit Chair of Advanced Computing in ECE and a Georgia Research Alliance (GRA) Eminent Scholar. “We are grateful to Samsung for their continued support, as we work towards the next milestone.”

Looking for Collective Solutions to Shared Challenges

According to Das, the approach not only demonstrates the capability to achieve reduced voltage and enhanced memory but also aligns with scalability and broad industry adoption. 

As the project ventures into commercial avenues, the input of Samsung's researchers will be crucial. Das and Park are actively uncovering the intricacies of disturbances that could impede the market acceptance of the new gate stack.

In this context, disturbances refer to any unintended disruptions or deviations from transistor behavior expectations. Das stresses the importance of understanding, controlling, and clearly defining disturbance specifications. Establishing a well-defined threshold for disturbances is pivotal for achieving widespread commercialization readiness in their research.

“Working alongside industry leaders like Samsung is essential for any endeavor aiming to make a transformative impact in everyday technology,” added Khan. “It becomes particularly pertinent as we collectively look towards a future dominated by the power required to fuel advancements in AI.”
 

Citation: Dipjyoti Das*, Hyeonwoo Park*, Zekai Wang, Chengyang Zhang, Prasanna Venkatesan Ravindran, Chinsung Park, Nashrah Afroze, Po-Kai Hsu, Mengkun Tian, Hang Chen, Winston Chern, Suhwan Lim, Kwangsoo Kim, Kijoon Kim, Wanki Kim, Daewon Ha; Shimeng Yu, Suman Datta, Asif Khan. “Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications.” Proceedings of the 2023 IEEE International Electron Devices Meeting (IEDM). Paper # 24.1

Since 2016, Tentzeris has held the Ken Byers Professorship in flexible electronics in ECE. He joined the faculty in 1998 and leads the ATHENA Research Group.

Ed Joy, co-namesake of the endowment with his wife Pat, holds the title of professor emeritus in ECE. His tenure as a professor of electrical engineering in the School spanned from 1970 to 1998, with a specialization in near-field antenna measurements.

Tentzeris,a noteworthy first recipient of the title, boasts an extensive research portfolio covering many domains. His expertise spans 3D Printed RF electronics, antennas and modules, flexible and conformal electronics an phased antenna arrays up to sub-THz, origami and morphing electromagnetics, Highly Integrated/Multilayer Packaging for RF and Wireless Applications using ceramic and organic flexible materials, “green” paper-based RFIDs and sensors, nanostructures for RF, wireless sensors, energy harvesting and wireless power transfer/wireless power grids, reconfigurable intelligent metasurfaces, heterogeneous integration and SOP-integrated (UWB, multiband, conformal) antennas.

His body of work includes more than 850 papers in refereed Journals and Conference Proceedings, 5 books and 25 book chapters. Recognized for his significant contributions to wireless communications encompassing additively manufactured antenna arrays and RF modules as well as wireless power transfer, wireless sensors and microlocalization/RFIDs, he has been awarded three significant research accolades in recent years:

• 2022 Georgia Tech Outstanding Doctoral Thesis Advisor Award
• 2021 IEEE Antennas and Propagation Symposium (APS) Best Student Paper Award
• 2021 "5G as a Wireless Grid" technology was featured as one of the World Economic Forum’s Top 10 Emerging Technologies of 2021.

His influence extends beyond the Georgia Tech, as Tentzeris has served as a Distinguished Lecturer for three IEEE societies: IEEE Microwave Theory and Technology Society (MTT), the IEEE Council on Radio Frequency Identification, and IEEE Electronic Packaging Society (EPS), where he currently lectures.

In recognition of his exceptional contributions to flexible hybrid electronics and multilayer RF Modules, Tentzeris was honored as an IEEE Fellow by the Microwave Theory and Techniques in 2010 as well as a Fellow of the Electromagnetics Academy.

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The College of Engineering’s Staff Culture Advisory Council (COESCAC) awarded Mitsuko Ito with this year’s Culture Champion Award in the School of Electrical and Computer Engineering (ECE). 

A Culture Champion winner for each College of Engineering (CoE) school was announced at this year’s CoE Staff Engagement Day event on November 15.

Ito, an academic program manager who supports the Vertically Integrated Projects program, is very involved in staff development and wellness initiatives. She is a licensed massage therapist, an accredited certified practitioner of the tapping technique, and includes “Well-being Activator” as part of her title in ECE.

She is recognized on campus for her Mindfulness-Based Stress Reduction (MBSR) and tapping sessions, available to Georgia Tech students, faculty, and staff. Tapping involves targeting 12 meridian points on the body to alleviate the effects of negative experiences or emotions. 

Thanks to the enthusiasm and backing from the campus community, Tapping @ GT has a straightforward protocol that anyone can easily pick up. Its positive impacts were particularly evident during the challenging times of the pandemic. Recently she has teamed up with Christian Gallie, the ECE Culture Champion from last year, to secure approval from the Student Government Association Mental Health Joint Allocation Committee (MHJAC) to expand outreach efforts and provide additional stress management and overall wellbeing support to students.

Since joining Georgia Tech in 2017, she has proven to be an invaluable resource, consistently infusing campus with positive energy.

Chance Brown, the director of financial administration in CoE, said of Ito:
Teamwork and mental health are something that Mitsuko takes seriously. She is dedicated to promoting a healthy lifestyle and providing stress relief techniques to faculty and staff at many of ECE’s events. Mitsuko makes the atmosphere more inclusive and harmonious.   

Linda Dillon, the assistant director of business operations in ECE, added:
One of the most commendable aspects of Mitsuko’s work is her tireless dedication to promoting mental health and provides effective stress-relief techniques such as tapping to the faculty and staff at many of our events. 

Read a Q&A with Mitsuko to learn more about her approach to mindfulness and EFT Tapping.

Kippelen, the current vice provost for International Initiatives and the Steven A. Denning Chair for Global Engagement, received the award in a ceremony at the Residence of France in Atlanta on November 6, 2023. 

The President of the French Republic had previously conferred the honor upon this year’s civilian recipients on June 2, 2023. The National Order of Merit is the second national Order of France after the Legion of Honor. Its purpose is to, “reward ‘distinguished merit’ and encourage the lifeblood of the country.” 

“On behalf of the Georgia Tech community, I extend my heartfelt congratulations to Bernard, a true science diplomat, who has made extraordinary contributions to research and to strengthening ties between the United States and France” said Georgia Tech President Ángel Cabrera. “Georgia Tech is indebted to him for all he has done and continues to do to enhance our reach, reputation, and impact on the global stage." 

During the award ceremony, John McIntyre, the founding executive director of the Georgia Tech Center for International Business Education and Research (CIBER), bestowed the medal upon Kippelen. President Cabrera and Anne-Laure Desjonquères, the consul general at Consulate of France in Atlanta, were joined by Kippelen's family, friends, and colleagues at the ceremony. 

“Professor Kippelen has been instrumental in fostering collaborations and partnerships and facilitating researcher and student mobility between France and the Southeast,” said Desjonquères. “The French consulate is profoundly grateful to Bernard Kippelen for his invaluable support to our annual series of events France-Atlanta, as well as to our exchange and mobility programs.” 

Kippelen joins Yves Berthelot (vice provost for International Initiatives, retd.), Marta H. Garcia (associate vice president for Development), and Steve McLaughlin (provost and executive vice president for Academic Affairs) as fellow Georgia Tech recipients of the Knight of the French National Order of Merit distinction.  

In 2003, Bernard joined the Georgia Tech faculty and served as director of the Center for Organic Photonics and Electronics (COPE) from 2011-2019. He is a co-founder and co-president of the Institut Lafayette, an innovation platform located at Georgia Tech-Europe in Metz, France. 

While at Georgia Tech, he has worked with the Office for Science and Technology (OST) of the Embassy of France to support the Technology Venture Accelerator (NETVA) program established to develop technological partnerships in the United States for young and innovative French startups. 

Kippelen was raised in Soultz, Alsace, France, and is a U.S. and French citizen. He studied at the University Louis Pasteur in Strasbourg, France (Ph.D. 1990) and was a member of the Centre National de la Recherche Scientifique (CNRS). Before joining Georgia Tech, he was on the faculty of the Optical Sciences Center at the University of Arizona. 

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Top photo caption:
Bernard Kippelen receiving the Knight of the French National Order of Merit on Nov. 6, 2023 at the Residence of France in Atlanta. In the photo are (L-R): Yves Berthelot, Beth Cabrera, Ángel Cabrera, Virginie Kippelen, Bernard Kippelen, Steve McLaughlin, Marta H. Garcia, John McIntyre, and Anne-Laure Desjonquères. 

Since becoming a part of the Georgia Tech faculty in 2012, where he holds a joint appointment in Materials Science and Engineering, Cai has played a pivotal role in advancing research on nanophotonic materials and devices. Notably, his authored work, "Optical Metamaterials: Fundamentals and Applications," serves as a globally recognized textbook and reference.

Cai's accolades include the OSA/SPIE Joseph W. Goodman Book Writing Award, the CooperVision Science & Technology Award, and the Office of Naval Research Young Investigator Award. He is also a Fellow of SPIE, the international society for optics and photonics.

Optica Fellows, a select group representing no more than 10 percent of the total membership, are individuals who have demonstrated exceptional dedication to advancing optics and photonics. The election process is highly competitive, with candidates recommended by the Fellow Members Committee and subsequently approved by the Awards Council and Board of Directors.

Alongside 128 other distinguished individuals, Cai will be honored at Optica conferences and events throughout 2024. The comprehensive list of the 2024 Optica Fellows is accessible online.

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Professor Douglas Blough and Ph.D. candidate Jingyuan Zhang have received the Best Paper Award at this year’s IEEE Conference on Local Computer Networks (LCN).

Blough, who has been a part of the Georgia Tech School of Electrical and Computer Engineering (ECE) faculty since 1999, currently holds the position of associate chair for faculty development. Zhang contributes to groundbreaking research as a member of the Critical Networking Laboratory led by Blough. Their focus lies in developing and evaluating advanced networks and systems, incorporating the latest breakthroughs in physical-layer networking.

The prizewinning paper, titled "Enhancing Coverage in Intelligent-Surface-Assisted mmWave WLANs through Multi-Hop Communication Analysis," tackles a crucial issue in the upcoming era of wireless networks that harness the millimeter-wave (mmWave) spectrum—specifically, the challenge of mitigating signal blockage inherent in mmWave frequencies.

One promising technology that can be used for this purpose is the reconfigurable intelligent surface (RIS), which can flexibly relay signals around obstacles when placed at strategic locations in the environment. The paper quantifies the improvement in mmWave wireless coverage that results from the use of RISs in single-RIS and multi-RIS link configurations. The results shed light on the relationship among connection probability of communication links, link budget parameters, RIS distribution, and obstacle distribution. The findings can help guide future mmWave network deployments to minimize the impacts of blockages on network performance and provide seamless operation to users in next-generation networks.

The paper stood out among 105 submissions during the 48th IEEE LCN held in Daytona Beach, Fla., in October. The conference is renowned as the premier event addressing both theoretical and practical aspects of local computer networks. 

Serving as the Steve W. Chaddick School Chair in the Georgia Tech School of Computer and Electrical Engineering since 2021, Raychowdhury completed his Ph.D. in ECE at Purdue in 2007 and joined Georgia Tech ECE as an associate professor in 2013.

His noteworthy contributions to the semiconductor industry include designing the world's first adaptive echo-cancellation network for integrated DSLs at Texas Instruments. Additionally, he played a pivotal role in developing foundational technologies in memory and logic design at Intel, widely adopted across the industry.

During the 31st annual OECE awards ceremony earlier this month, the Elmore Family School of Electrical and Computer Engineering honored six accomplished alumni, including Raychowdhury. Purdue ECE established the OECE award in 1992 to acknowledge the professional achievements of top graduates, expressing appreciation for the recognition these accomplishments bring to both Purdue and the School.
 

Top photo caption: Arijit Raychowdhury (right) receiving the Purdue ECE OECE award from Milind Kulkarni, interim head of the Elmore Family School of Electrical and Computer Engineering. (Purdue University photo)

The team is comprised of Professor Greg Durgin and graduate students Vaibhav Bhosale, Jonathan Dolan, Grishma Kalepu, and Deeksha Manjunath. Their award-winning paper, “PaddleSats: Attitude Control and Station-Keeping for Ultra-Low Density SSP Satellites,” was selected from a field of 37 international papers.

The research presents the authors’ new PaddleSat concept in which satellites are constructed from uniformly thin surfaces, using deflections in their solar panels and subsequent changes in solar pressure-induced momentum to perform station-keeping operations. Such satellites have low launch costs and very long lifetimes in space, as there is no longer the need to carry station-keeping fuel.

PaddleSats also mitigate space debris concerns as the uniformly thin satellites will—without intervention from their controller—gradually descend from orbit (either in fragments or as a whole) due to the influence of solar pressure on the spacecraft. The PaddleSat concept is crucial for developing space solar power satellites for green energy or even low-cost communication satellites that do not contribute long-term orbital debris.

The four students who co-authored the paper began investigating the concept in 2022 as an “ECE 6390 Satellite Communications and Navigation Systems” course project. They continued to refine their work after the course, which led to this original, award-winning concept paper.

The IEEE WiSEE international conference series has been a home for the top-tier research in wireless-related systems in space for the last 11 years. The researchers were honored at this year’s conference held in Aveiro, Portugal from September 6-8.

Top photo caption: Student researchers Vaibhav Ghosale (middle) and Grishma Kalepu (right) being presented the WiSEE Best Paper Award from Juan Fraire, the conference’s technical program committee chair.

Launched by MLCommons this year, the Machine Learning and Systems Rising Stars initiative was created to identify and support a cohort of current and recently graduated Ph.D. students specializing in machine learning and systems in order to develop community, foster research and career growth, and enable collaborations across academia and industry. This year 35 early-to-late-stage and recently graduated Ph.D. were selected as Rising Starts from over 100 applicants from dozens of global universities.

Wan is advised by ECE professors Arijit Raychowdhury and Tushar Krishna. His research interests center around computer architecture, VLSI, and embedded systems, with a focus on building hardware and systems for cognitive intelligence and autonomous machines (such as robots, drones, and unmanned vehicles), aiming to advance their performance, efficiency, resilience, and trustworthy.

A highlight of Wan’s work is his award-winning research, “Intelligence in Robotic Computing: Agile Design Flows for Efficient and Resilient Autonomous Machines.” Through synergistic advances in systems, hardware architectures, solid-state technologies, and collective intelligence, Wan led a team in developing an efficient and adaptive hardware accelerator, resilient and robust system optimization, and agile and scalable design methodology for autonomous machine computing.

His research has been recognized by the ECE Graduate Research Assistant (GRA) Excellence Award in 2023, IEEE Micro Top Picks Honorable Mention in 2023, first place in ACM Student Research Competition in 2022, the CRNCH Ph.D. Fellowship in 2022, and the Best Paper Award from the IEEE/ACM Design Automation Conference (DAC) in 2020.

As part of the Machine Learning and Systems Rising Star cohort, Wan presented at this year’s rising star program at Google, Mountain View, CA on Aug. 17-18, 2023.

In addition to Wan, three other Georgia Tech Ph.D. students were recognized as Machine Learning and Systems Rising Stars: Yonggan Fu, Haoran You, and Yang (Katie) Zhao, all in the College of Computing.

The Intel Rising Star Faculty Award (RSA) program annually recognizes early-career academic researchers who are at the forefront of technological research with the potential to reshape industries. The program provides both a monetary award and hopes to facilitate long-term collaborative relationships with senior technical leaders at Intel. Award recipients are also chosen for their innovative teaching methods and for their efforts to improve the fields of computer science and engineering.

Hao joined the ECE the faculty in 2022 and she currently holds the Sutterfield Family Early Career Professorship. She received her Ph.D. in electrical engineering from Waseda University, Japan, in 2017, and was a postdoc in UIUC from 2018 to 2021.

She supervises six Ph.D. students in the Software/Hardware Co-design (Sharc) Lab, exploring the joint area of efficient hardware design, machine learning algorithms, and agile design automation tools. The group's work involves high-performance graph neural network (GNN) accelerator design and automation, which are highly recognized and broadly used by high energy physicists, winning the 2023 International Conference on Field-Programmable Logic and Applications (FPL) community award for impactful open-source contributions. Her group also focuses on building open-source design automation tools, especially high-level synthesis, significantly expediting hardware and architecture development; one of their works was awarded IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) best paper runner-up.

ECE’s Asif Khan was recognized with an Intel Rising Star Award in 2020.

Xi's winning paper, titled “Maximum Power-Point Theory for Thermoelectric Harvesters,” shows how linear losses in the energy-harvesting circuit that draws power from the thermoelectric source reduce the direct current voltage of the source and quadratic losses raise the series resistance. This phenomenon not only decreases the power delivered to the load but also shifts the maximum power point of the system. With the model developed by Xi, engineers can more easily and more effectively design thermoelectric harvesters so they output the highest power possible.

Swaminathan is professor emeritus in the Georgia Tech School for Electrical and Computer Engineering (ECE) and the current department head of electrical engineering in the Penn State School of Electrical Engineering and Computer Science (EECS).

For 28 years, Swaminathan dedicated his career to Georgia Tech, becoming the director of the 3D Systems Packaging Research Center (PRC) in 2019. The establishment of the PRC was led by Rao Tummala, the namesake of the Electronics Packaging Technology Award, and also professor emeritus in ECE. Swaminathan played a pivotal role in the advancement of the PRC while at Georgia Tech.

The award is one of IEEE’s Technical Field Awards (TFAs) which represents the highest award given by each IEEE Society, bestowed for contributions or leadership in specific fields of interest of IEEE.

The distinguished award, sponsored by the IEEE Electronics Packaging Society and Friends of Rao R. Tummala, acknowledges Swaminathan’s, “exceptional contributions to semiconductor packaging and system integration technologies, which have significantly improved electronic system performance, efficiency, and capabilities.”

In 2023, Swaminathan joined the Penn State faculty as the William E. Leonhard Endowed Chair. He also serves as the director of the Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES), supported through Semiconductor Research Corporation (SRC)’s Joint University Microelectronics Program 2.0 (JUMP 2.0).

Tummala was the Joseph M. Pettit Chair in Electronics Packaging in ECE from 1993 to 2019. As the founding director of PRC, he pioneered the Second Law of Electronics, propelling the industry forward with his visionary System-On-Package (SOP) concept. His contributions were further recognized with the distinguished title of Georgia Research Alliance Eminent Scholar from 1993 to 2019.

Top photo: Madhavan Swaminathan (left) and Rao R. Tummala (right).