{"637117":{"#nid":"637117","#data":{"type":"event","title":"PhD Defense by Prasanth Chatarasi","body":[{"value":"\u003Cp\u003ETitle: Advancing Compiler Optimizations for General-Purpose and Domain-Specific Parallel Architectures\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EPrasanth Chatarasi\u003C\/p\u003E\r\n\r\n\u003Cp\u003EPh.D. Candidate\u003C\/p\u003E\r\n\r\n\u003Cp\u003ESchool of Computer Science\u003C\/p\u003E\r\n\r\n\u003Cp\u003ECollege of Computing\u003C\/p\u003E\r\n\r\n\u003Cp\u003EGeorgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Ca href=\u0022https:\/\/pchath.github.io\/gatech-webpage\/\u0022\u003Ehttps:\/\/pchath.github.io\/gatech-webpage\/\u003C\/a\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDate: Monday, July 27th, 2020\u003C\/p\u003E\r\n\r\n\u003Cp\u003ETime: 10:00 AM \u0026ndash; 12:00 PM ET\u003C\/p\u003E\r\n\r\n\u003Cp\u003ELocation:\u0026nbsp;\u003Ca href=\u0022https:\/\/bluejeans.com\/vsarkar9\u0022\u003Ehttps:\/\/bluejeans.com\/vsarkar9\u003C\/a\u003E\u0026nbsp;(remote)\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003ECommittee:\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Vivek Sarkar (Advisor), School of Computer Science, Georgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Jun Shirako (Co-Advisor),\u0026nbsp;School of Computer Science, Georgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Tushar Krishna,\u0026nbsp;School of Electrical and Computer Engineering, Georgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Santosh Pande, School of Computer Science,\u0026nbsp; Georgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Richard Vuduc, School of Computational Science and Engineering,\u0026nbsp;\u0026nbsp;Georgia Institute of Technology\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EAbstract:\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u0026mdash;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EComputer hardware is undergoing a major disruption as we approach the end of Moore\u0026rsquo;s\u0026nbsp;law, in the\u0026nbsp;form of new advancements to general-purpose and domain-specific parallel architectures.\u0026nbsp;Contemporaneously, the demand for higher performance is broadening across\u0026nbsp;multiple application\u0026nbsp;domains ranging from scientific computing applications to deep learning and graph analytics. These\u0026nbsp;trends raise a plethora of challenges to the de-facto approach\u0026nbsp;to achieving higher performance, namely\u0026nbsp;application development using high-performance\u0026nbsp;libraries. Some of the challenges include\u0026nbsp;porting\/adapting to multiple parallel architectures, supporting rapidly advancing domains, and also\u0026nbsp;inhibiting optimizations across library calls. Hence, there is a renewed focus on advancing optimizing\u0026nbsp;compilers from\u0026nbsp;industry and academia to address the above trends, but doing so requires enabling compilers to work effectively on a wide range of applications and also to exploit current and\u0026nbsp;future parallel\u0026nbsp;architectures better. As summarized below, this thesis focuses on compiler\u0026nbsp;advancements for current and\u0026nbsp;future hardware trends.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EFirst, we observe that software with explicit parallelism for general-purpose multi-core\u0026nbsp;CPUs and GPUs\u0026nbsp;is on the rise, but the foundation of current compiler frameworks is based\u0026nbsp;on optimizing sequential code.\u0026nbsp;Our approach uses explicit parallelism specified by the programmer as logical parallelism to refine the\u0026nbsp;conservative dependence analysis inherent in\u0026nbsp;compilers (arising from the presence of program constructs\u0026nbsp;such as pointer aliasing, unknown function calls, non-affine subscript expressions, recursion, and\u0026nbsp;unstructured control\u0026nbsp;flow). This approach makes it possible to combine user-specified parallelism and\u0026nbsp;compiler-generated parallelism in a new unified polyhedral compilation framework (PoPP).\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cbr \/\u003E\r\nSecond, despite the fact that compiler technologies for automatic vectorization for\u0026nbsp;general-purpose\u0026nbsp;vector processing (SIMD) units have been under development for over\u0026nbsp;four decades, there are still\u0026nbsp;considerable gaps in the capabilities of modern compilers to\u0026nbsp;perform automatic vectorization. One such\u0026nbsp;gap can be found in the handling of loops with\u0026nbsp;dependence cycles that involve memory-based anti\u0026nbsp;(write-after-read) and output (write-after-write) dependences. A significant limitation in past work is the\u0026nbsp;lack of a unified\u0026nbsp;formulation that synergistically integrates multiple storage transformations to break the\u0026nbsp;cycles and further unify the formulation with loop transformations to enable vectorization.\u0026nbsp;To address\u0026nbsp;this limitation, we propose the PolySIMD approach.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThird, the efficiency of domain-specific spatial accelerators for Deep Learning (DL) solutions depends\u0026nbsp;heavily on the compiler\u0026rsquo;s ability to generate optimized mappings or code\u0026nbsp;for various DL operators\u0026nbsp;(building blocks of DL models, e.g., CONV2D, GEMM) on the\u0026nbsp;accelerator\u0026rsquo;s compute and memory\u0026nbsp;resources. However, the rapid emergence of new operators and new accelerators pose two key challenges\/requirements to the existing compilers: 1) Ability\u0026nbsp;to perform fine-grained reasoning of various algorithmic aspects of the new\u0026nbsp;operators and also complex\u0026nbsp;hardware structures of the new accelerators to achieve peak\u0026nbsp;performance, and 2) Ability to quickly\u0026nbsp;explore the enormous space of possible mappings\u0026nbsp;involving various partitioning schemes, loop\u0026nbsp;transformations, and data-layout choices, yet\u0026nbsp;achieving high-performance and energy efficiency. To\u0026nbsp;address these challenges, we introduced a data-centric compiler \u0026ldquo;Marvel\u0026rdquo; for optimizing DL operators\u0026nbsp;onto flexible spatial\u0026nbsp;accelerators. We also introduced a high-performance vectorizing compiler \u0026ldquo;Vyasa\u0026rdquo;\u0026nbsp;for\u0026nbsp;optimizing tensors convolutions on specialized SIMD units of Xilinx AI Engine.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cbr \/\u003E\r\nFinally, with the emergence of a domain-specific thread migratory architecture (EMU)\u0026nbsp;to address the\u0026nbsp;locality wall, we developed thread-migration aware compiler optimizations\u0026nbsp;to enhance the performance\u0026nbsp;of graph analytics on the EMU machine. Our preliminary\u0026nbsp;evaluation of compiler optimizations such as\u0026nbsp;node fusion and edge flipping demonstrates a\u0026nbsp;significant benefit relative to the original programs.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Advancing Compiler Optimizations for General-Purpose and Domain-Specific Parallel Architectures"}],"uid":"27707","created_gmt":"2020-07-20 17:40:45","changed_gmt":"2020-07-20 17:40:45","author":"Tatianna Richardson","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2020-07-27T11:00:00-04:00","event_time_end":"2020-07-27T13:00:00-04:00","event_time_end_last":"2020-07-27T13:00:00-04:00","gmt_time_start":"2020-07-27 15:00:00","gmt_time_end":"2020-07-27 17:00:00","gmt_time_end_last":"2020-07-27 17:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"221981","name":"Graduate Studies"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78761","name":"Faculty\/Staff"},{"id":"78771","name":"Public"},{"id":"174045","name":"Graduate students"},{"id":"78751","name":"Undergraduate students"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}