{"634313":{"#nid":"634313","#data":{"type":"event","title":"Ph.D. Proposal Oral Exam - Siddharth Ravichandran","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle:\u0026nbsp; \u003C\/strong\u003E\u003Cem\u003EDesign \u0026amp; Demonstration of 3D Glass Panel Embedded Package for Superior Bandwidth and Power Efficiency\u003C\/em\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee:\u0026nbsp; \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Tummala, Advisor\u0026nbsp;\u0026nbsp;\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Naeemi, Chair\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Swaminathan\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Peterson\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Smet\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract: \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe objective of the proposed research is to model, design and demonstrate a novel 3D embedded package technology for next-generation high-performance computing (HPC) systems. The proposed research focuses on the following objectives: (1) design a 3D package to achieve \u0026gt;1 Tbps bandwidth at \u0026lt;1 pJ\/bit power-efficiency and (2) develop materials and processes to fabricate and demonstrate such a package.\u0026nbsp;With the slowing down of Moore\u0026#39;s law scaling, HPC systems today pursue heterogeneous integration of logic and memory chips on the package. Hence, the bandwidth and power-efficiency (measured as energy-per-bit) of chip-to-chip communication becomes the limiting factor in scaling system performance. These two key metrics are primarily driven by I\/O count, interconnect length, wiring density and the choice of dielectric materials. Today, the technology options for package-level integration in HPC are either 2.5D\/3D and chip-first\/chip-last architectures. While 3D and chip-first technologies solve the interconnect length and I\/O count challenges respectively, they are still fundamentally limited in scaling the driving factors for bandwidth and power-efficiency comprehensively. This research proposes a novel chip-first 3D packaging technology using glass-based panel embedding to simultaneously address I\/O density and interconnect length while utilizing low-dk\/df materials and low-loss polymer RDL technologies. Through modeling and characterization, the electrical design of such a system will be studied. A design-space exploration of key substrate parameters to assess the bandwidth and energy-per-bit potential of proposed structure will also be conducted and benchmarked against state-of-the-art technology options. The materials and processes will be studied and a stable fabrication process flow will be established to demonstrate such a 3D package in a panel-scalable, low-cost and thermo-mechanically reliable fashion.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Design \u0026 Demonstration of 3D Glass Panel Embedded Package for Superior Bandwidth and Power Efficiency"}],"uid":"28475","created_gmt":"2020-04-13 17:53:59","changed_gmt":"2020-04-13 17:53:59","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2020-04-23T11:00:00-04:00","event_time_end":"2020-04-23T13:00:00-04:00","event_time_end_last":"2020-04-23T13:00:00-04:00","gmt_time_start":"2020-04-23 15:00:00","gmt_time_end":"2020-04-23 17:00:00","gmt_time_end_last":"2020-04-23 17:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434371","name":"ECE Ph.D. Proposal Oral Exams"}],"categories":[],"keywords":[{"id":"102851","name":"Phd proposal"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}