Ph.D. Thesis Defense

Sriseshan Srikanth

Ph.D. Candidate

School of Computer Science

College of Computing

Georgia Institute of Technology

Date: Monday, March 2, 2020

Time: 10:00 AM to 12:30 PM Eastern Time

Location: KACB 3126

Committee:

Dr. Thomas M. Conte, Advisor, School of Computer Science Dr. Hyesoon Kim, School of Computer Science Dr. Tushar Krishna, School of Electrical and Computer Engineering Dr. Vivek Sarkar, School of Computer Science Dr. Erik P. DeBenedictis, Zettaflops, LLC

Abstract:

An increasing prevalence of data-irregularity is being seen in applications today, particularly in machine learning, graph analytics, high-performance computing and cybersecurity. Faced with fundamental technology constraints, architectures that have been designed around conventional assumptions on spatio-temporal locality are inefficient for these important domain areas. In this defense, I will provide an overview of my PhD thesis that proposes architectures to improve energy efficiency and performance by intelligently reducing data movement through the memory hierarchy for such data-irregular applications.

In particular, this talk will focus on near-memory acceleration of hyper-sparse data applications as well as processor-centric acceleration of moderately-sparse applications. Through novel sparse data representations, algorithms and programmable hardware, both of these approaches extract sequential locality from a dynamic, sparse data stream via intelligent data marshaling. As a result, an order of magnitude improvement in cache bandwidth utilization and reduction in DRAM row activations is seen across several sparse workloads, thus contributing to significant performance and energy benefits.