Committee:

Dr. Hyesoon Kim, CS, Chair , Advisor

Dr. Thomas Conte, ECE

Dr. Saibal Mukhopadhyay, ECE

Dr. Tushar Krishna, ECE

Dr. Richard Vuduc, CS

Dr. Jefffrey Young, CoC

Abstract:

This work concerns a generative hardware description library for C++, the CHDL Hardware Design Library or CHDL, along with a body of supporting libraries and a description of a core design implemented using this library. The supporting libraries extend the level of abstraction covered by CHDL from the solely constructive and generative to a range of hardware description paradigms including the register transfer level (RTL), an implementation of Bluespec-like guarded atomic actions (GAA), and a novel pipeline-oriented HDL providing a high-level synthesis flow from algorithmic descriptions of pipelined hardware. Design input using all of these paradigms is converted by CHDL into an in-memory gate level netlist that may be simulated, emitted as synthesizable Verilog, or technology mapped to a standard cell library for area and energy estimation. Access to this netlist, dubbed “netlist introspection”, is provided by the CHDL API, allowing novel optimizations and transformations to be performed by the designer.