Committee:

Dr. Madhavan Swaminathan, ECE, Chair , Advisor

Dr. Sung-Kyu Lim, ECE

Dr. Arijit Raychowdhury, ECE

Dr. Saibal Mukhopadhyay, ECE

Dr. Suresh Sitaraman, ME

Abstract:

The objective of this dissertation is to develop time-domain behavioral models for I/O drivers and oscillators for fast simulation and IP protection. For oscillators, augmented neural networks (AugNNs) are proposed to capture the oscillatory behavior of fixed-frequency oscillators and VCOs. When output buffer is included as a part of the oscillator circuit, AugNN-based models are developed taking into account the I/O behavior of the oscillator. For tunable drivers with pre-emphasis, state-aware weighting functions are proposed, and the dynamic memory characteristics of the driver’s output stage are captured using recurrent neural networks (RNNs). The behavior of the tunable control parameters is captured. Furthermore, a transition-variational model is discussed for the modeling of I/O drivers under overclocking conditions. The proposed models are compatible with Verilog-A.