Li is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE), where he is a member of the Integrated 3D Systems Group. He received the award for his poster, “Low temperature, pressure-less, and misalignment tolerant bonding processes for extreme fine pitch interconnects.” Co-contributors to the poster include ECE Professor Muhannad Bakir, who is Li’s Ph.D. advisor; Sreejith Rajan, a Ph.D. student who is also advised by Bakir and Gary May, the chancellor of the University of California at Davis and ECE adjunct faculty member; and Muneeb Zia, who is a research engineer II in ECE. 

Monolithic integrated circuits (ICs) have progressed at an unprecedented rate of innovation in the past 60 years. However, with Moore's Law slowing down, 'polylithic' integration of heterogeneous ICs (or chiplets) is projected to be a key driver for performance, power, and cost in the next era of Moore’s Law. The objective of the research is to explore ultra-high density chip inputs/outputs (I/O) using approaches fundamentally different from those used today in the commercial arena. The end goal is to demonstrate sub-micron I/O densities between bonded chips for extreme bandwidth densities in 3D and 2.5D polylithic ICs. Doing so unlocks a number of architectural innovations that can dramatically improve energy efficiency and performance of electronic computing systems.

The mission of ASCENT is to provide breakthrough advances in integrated nanoelectronics to sustain the promise of Moore’s Law. Led by Notre Dame, along with 13 partner universities and 29 principal investigators, the Center is funded for $49 million over five years.