Committee:

Dr. Sung Kyu Lim, ECE, Chair , Advisor

Dr. Saibal Mukhopadhyay, ECE

Dr. Arijit Raychowdhury, ECE

Dr. Tushar Krishna, ECE

Dr. Hyesoon Kim, CoC

Abstract:

The wafer-level 3D integration including face-to-face (F2F) and monolithic 3D (M3D) technologies has been featured as a promising innovation to succeed the horizontal device scaling benefit in the looming end of Moore's law. The objective of this research is two-fold: Firstly, to develop computer-aided-design (CAD) methodologies to address potential issues of the wafer-level 3D integration including power integrity, inter-tier variations, and cost overhead. Secondly, to evaluate the PPA benefits of the wafer-level 3D integration to the neuromorphic processor design at the full-chip level by applying proposed solutions. For the first part, the static power integrity issue of transistor-level M3D ICs is inspected in detail, and we address the issue by proposing a new layout scheme for transistor-level M3D standard cells. Next, physical design solutions for gate-level M3D ICs are developed to mitigate the negative impact of inter-tier device and interconnect variations, as well as the cost overhead issue. In addition, we present the unique physical design solution named Compact-2D flow, which produces commercial-quality gate-level F2F IC layouts. For the second part, we adopt the liquid-state-machine architecture, a model of recurrent spiking neural networks, to build an online machine-learning hardware platform, and study the PPA benefits of gate-level F2F and M3D ICs on the non-trivial real-world speech recognition application. This work serves as an important step towards realizing bio-inspired neuromorphic processors utilizing 3D IC design advantages.