Committee:

Dr. Stevenson Kenney, ECE, Chair , Advisor

Dr. Stephen Ralph, ECE

Dr. Gregory Durgin, ECE

Dr. Richard Causey, ECE

Dr. Paul Kohl, ChBE

Abstract:

This research presents circuit-level solutions for frequency synthesis and other time-domain signal processing problems. Specifically, three circuit architectures are proposed: a hybrid digital and analog phase-locked loop architecture that is capable of suppressing reference and VCO phase noise simultaneously, a VCO architecture that eases tradeoffs between ring VCOs and LC VCOs, and a time-to-digital converter with a sample-and-hold mechanism, dynamic element matching and quantization noise scrambling.