Learning electrical and computer engineering has always come with a unique challenge: many of its foundational concepts — electric fields, magnetic forces, semiconductor behavior — are invisible to the naked eye and difficult to visualize.
To make these invisible principles tangible, students in the School of Electrical and Computer Engineering have long used specialized tools and software. Circuit simulators model voltage and current, electromagnetic tools visualize fields, and semiconductor design platforms reveal transistor behavior. These tools turn abstract theory into interactive experiences that prepare students for real-world engineering challenges.
Now, Apple Vision Pro is joining this ecosystem.
The technology introduces spatial computing to learning environments, blending digital content with the physical world.
At the Institute for Matter and Systems, infrastructure lead Alex Gallmon, is collaborating with students and industry partners to create immersive digital twins—virtual models that replicate real-world systems—of semiconductor cleanroom equipment.
“These machines are complex and costly, with parts that can run tens of thousands of dollars,” he said. “Even minor mistakes during operation can lead to expensive damage or downtime.”
Gallmon's team built a virtual replica of a cleanroom vacuum training system. The project serves as a prototype for a workforce development program aimed at high school and college students interested in careers in the semiconductor or vacuum technology fields.
Read the full story from the School of Electrical and Computer Engineering
Spatial computing is transforming engineering education at Georgia Tech and opening new paths for entrepreneurship and technical training.
Gallmon showing how Apple Vision Pro can be utilized to train students and workers on sensitive and expensive technical equipment, in this case a cleanroom vacuum system.
The National Academy of Inventors is honoring two Georgia Tech faculty members for their contributions to technology and society: Deepakraj “Deepak” Divan and Arijit Raychowdhury. Both are in the School of Electrical and Computer Engineering.
Raychowdhury is a semiconductor pioneer whose patented circuit and system-on-chip designs have advanced computing efficiency and commercialization. Divan is a global leader in power electronics and grid modernization, whose innovations and ventures have transformed how electricity is delivered and managed worldwide.
“Congratulations to Deepakraj and Arijit on earning one of the most esteemed accolades in technology and discovery. Their groundbreaking work, with nearly 100 patents between them, advances solutions to global challenges,” said Raghupathy “Siva” Sivakumar, chief commercialization officer at Georgia Tech. “Their success exemplifies how research commercialization drives real-world impact, and we’re proud to see them honored as academy fellows.”
Election to NAI is the highest professional distinction specifically awarded to inventors. With this recognition, Georgia Tech’s roster of NAI Fellows grows to 24. Divan and Raychowdhury join a 2025 class of 169 new fellows representing university, government, and nonprofit organizations worldwide. They will be inducted at the NAI 15th Annual Conference on June 4, 2026, in Los Angeles.
Professor Emeritus (2004-2025)
Georgia Research Alliance Eminent Scholar
School of Electrical and Computer Engineering
Founder, Georgia Tech Center for Distributed Energy
Deepakraj “Deepak” Divan is a globally recognized innovator in power electronics and grid transformation. He was awarded the IEEE Medal in Power Engineering in 2024.
He holds over 85 U.S. and international patents and has authored 400 refereed publications. His pioneering work on soft‑switching converters—integral for efficient energy storage, EV charging, and industrial controls—has spurred a global $70 billion power electronics industry.
Divan laid the groundwork for grid‑forming inverter control, enabling high-renewables integration. He is the co-author of Energy 2040: Aligning Innovation, Economics and Decarbonization, named by Forbes as one of the “10 Essential Books and Podcasts Every Leader Needs in 2025”.
“Being named an NAI Fellow is a tremendous honor,” said Divan. “It reflects years of effort to rethink how electricity is delivered and managed to solve real problems and to drive practical innovations that matter.”
As the founder of Georgia Tech’s Center for Distributed Energy, he led research that transforms electricity delivery through analytics, monitoring, and optimization.
An entrepreneur, Divan co-founded Varentec (backed by Bill Gates and Khosla Ventures) and seeded ventures including GridBlock, Soft Switching Technologies, Innovolt, and Smart Wires—raising over $500 million. A National Academy of Engineering member and IEEE Fellow, he champions scalable energy-access solutions worldwide.
Professor and Steve W. Chaddick School Chair
School of Electrical and Computer Engineering
Director, Center for the Co-Design of Cognitive Systems
Arijit Raychowdhury has been the Steve W. Chaddick School Chair of ECE since 2021. He is a leading innovator in semiconductor technologies, holding more than 27 U.S. and international patents and authoring over 350 publications.
His work spans low-power circuits, specialized accelerators, and system-on-chip design, with breakthroughs widely adopted in industry.
“This recognition reflects the collective effort of students, colleagues, and partners who share a vision for advancing microelectronics,” said Raychowdhury. “I am honored that NAI champions the same mission to lead through research, education, and innovation."
At Texas Instruments, he developed the world’s first adaptive echo-cancellation network for integrated Digital Subscriber Lines (DSL)—a patented technology that enabled high-speed internet over traditional phone lines that received the EDN Innovation of the Year award. At Intel, he developed and incorporated foundational memory and logic technologies that shaped commercial products across global markets for more than a decade.
His research on fine-grain power management of systems-on-chip at Georgia Tech has been licensed and widely adopted by the semiconductor industry.
He directs Georgia Tech’s Center for the Co-Design of Cognitive Systems and leads initiatives to advance microelectronics design with applications to AI. Over the years, he has served as a founding advisor and board member to multiple startups in the areas of edge-computing and low power design.
Raychowdhury’s research bridges invention and real-world impact, earning him numerous honors, including IEEE Fellow, Semiconductor Research Corporation Technical Excellence Award, and multiple industry awards. Through pioneering designs and mentorship, he continues to drive innovation in computing systems, influencing both academic research and industrial commercialization.
As one of Georgia Tech’s 11 interdisciplinary research institutes, IMS is designed to break down silos between traditional academic units. By operating core user facilities and fostering collaborative research, IMS creates a unique ecosystem where device-level innovation meets systems-level design. This event personified that mission by connecting researchers who typically work on different ends of the stack.
“We’re looking for opportunities to bring people together to have discussions that are both informative and potentially create a little bit of friction in the best possible way around trending topics in science and engineering,” said Mike Filler, IMS deputy director, during opening remarks.
The panel was moderated by Divya Mahajan, assistant professor in the School of Electrical and Computer Engineering, and featured Moinuddin Qureshi, professor of computer science; Anand Iyer, assistant professor of computer science; and Asif Khan, associate professor in electrical and computer engineering.
The discussion explored the dynamics between compute abundance and energy constraints. As AI models scale up, power consumption has become a societal issue, driving up energy demands and even influencing political conversations. The panelists agreed that the bottleneck isn’t compute — a computer’s ability to process and execute tasks — but data movement. Moving data uses 100 to 1,000 times more energy than computation, making memory systems the critical frontier.
The conversation highlighted how breakthroughs in compute must occur at every layer — from individual devices to full computer systems. At the device level, Khan mentioned emerging memory technologies and “beyond CMOS” approaches such as embedding compute within memory and exploring bio-inspired architectures.
From a computer architecture level, Qureshi advocated rethinking interfaces and creating designs optimized for the future of computing. AI needs regular patterns to work optimally, and current patterns are not set up for that.
“If you want efficiency, design systems that make sense for AI,” Qureshi said. “Develop new interfaces, develop new modules, architectures, and organization that make for a specific pattern.”
At the systems level, Iyer stressed practical strategies like near-memory compute and energy-aware scheduling while acknowledging the need for co-design between hardware and software.
“Now in terms of brains or bio-inspired computing, my conjecture is that there is currently no hardware that is capable of doing it,” Khan said. He also noted that right now, there is no computer or algorithm that has the scale of computing comparable to human brain power.
The panelists didn’t shy away from provocative ideas — such as whether graphic processing units are the final solution for AI and whether matrix multiplication alone can lead to artificial general intelligence. While opinions varied, all agreed that organizations like IMS are key to bringing together diverse expertise to tackle these questions collaboratively.
The Boundaries and Breakthroughs series continues in January with a panel on bioelectronics and medical technologies, reinforcing IMS’s commitment to fostering dialogue that spans the full spectrum of innovation.
]]>The Institute for Matter and Systems
]]>The event marks the culmination of the semester-long I2P course, where undergraduate students develop functional prototypes aimed at solving real-world problems. Prototypes this semester include a smart military drone, a gentler device for cervical cancer screening, a rotating espresso station, tools to keep AI safe, compact data centers, systems that simulate cyberattacks to help companies strengthen their defenses, and many more.
The showcase is free and open to students, faculty, staff, and members of the local community.
Winning teams will receive prizes and a “golden ticket” into CREATE-X’s Startup Launch, a summer accelerator that provides optional seed funding, accounting and legal service credits, mentorship, and more to help students turn their prototypes into viable startups.
This is a free event, and refreshments will be provided. Register for the Fall 2025 I2P Showcase today!
]]>Marketing Strategist
]]>The Institute for Matter and Systems (IMS) has completed a major expansion of its cleanroom facilities, which now totals more than 23,000 square feet – solidifying its position as the largest academic cleanroom in the Southeast.
The expansion includes a newly constructed 2,000-square-foot ISO 6 cleanroom, designed to house an advanced packaging and 3D heterogeneous integration (3DHI) facility.
“As demand for cleanroom facilities continues to rise across academia and industry, this expansion strategically positions Georgia Tech to support national initiatives and advance global leadership in semiconductor packaging technologies,” said Gary Spinner, associate director of cleanroom and fabrication facilities at IMS.
This state-of-the-art space will be equipped with next-generation processing and inspection capabilities that represent the next generation of semiconductor manufacturing technology.
“The new facility, in conjunction with our existing Marcus facilities, will provide the campus community and our industry and government partners with the tools and capabilities to pursue revolutionary technologies in advanced packaging and 3D heterogeneous integration,” said Muhannad Bakir, Dan Fielder Professor in the School of Electrical and Computer Engineering and director of the 3D Systems Packaging Research Center (PRC). “These innovations will include developing radical advanced packaging and 3D stack architectures that seamlessly integrate electronics, photonics, power delivery, and thermal technologies.”
The PRC will use the new facility for advanced packaging research supported by multiple national programs and industry partnerships.
This robust infrastructure will support emerging applications in artificial intelligence, high-performance computing, and advanced mm-wave and photonic communications systems. By enabling the dense integration of multiple specialized chips within substrates and chip stacks, the pursued advanced packaging research will deliver more scalable, powerful and energy efficient systems at lower cost and shorter design cycles.
The Institute for Matter and Systems
]]>As microchips grow more complex and data demands intensify, traditional electrical connections are hitting their limits. Speed is king in today’s digital systems, but a major bottleneck remains in how quickly information can move between components like processors and memory.
This lag is one of the most pressing challenges in advanced hardware design. While processors continue to accelerate, the links that connect them can't keep pace.
Georgia Tech researcher Ali Adibi is addressing this problem with $5.3 million in funding over three years from the Defense Advanced Research Projects Agency (DARPA). His project is part of DARPA’s Heterogeneous Adaptively Produced Photonic Interfaces (HAPPI) program, which aims to dramatically boost the speed and density of data transmission within microsystems by using light instead of electricity.
“Optical solutions are highly advantageous for providing the required data rates and power consumptions, and our project is formed to address the most important challenges for achieving the system-level performance,” said Adibi, a professor and Joseph M. Pettit Chair in the School of Electrical and Computer Engineering.
The project brings together a multidisciplinary team, including collaborators from the Massachusetts Institute of Technology, University of Florida, NY CREATES, and NHanced Semiconductors, Inc.
Going Vertical
Unlike traditional optical communication, which connects systems across distances, this project focuses on enabling ultra-fast, low-loss communication withinelectronic systems.
The key innovation is vertically connecting electronic chips in a compact stack. This design helps overcome the limitations of planar optical routing geometries (layouts that guide light horizontally across a chip) which are often not compatible with the dense, 3D chip architectures needed for next-generation computing.
Adibi’s team is developing a novel 3D optical routing system that can transmit data with minimal loss, high bandwidth, and compact components. The system is designed to scale to large arrays of interconnected chips with minimal interference between data channels.
Smarter Design with Machine Learning
At the heart of the project is the use of machine learning (ML) to help design and optimize the light-based communication system.
ML is used to shape and fine-tune the tiny structures that guide light through and between chips. This includes finding the best sizes, shapes, and layouts for components like couplers and waveguides, so they can be made smaller, work more efficiently, and fit into dense chip layouts.
“Designing a complete, scalable 3D optical routing structure involves innumerable variables,” Adibi said. “Machine learning helps us navigate that complexity and find solutions that would be nearly impossible to identify manually.”
Tiny "Mirrors"
Another key innovation involves specialized optical structures, or what Adibi refers to as “artificial mirrors”.
The tiny, precisely shaped structures, called metagratings, are embedded in the chip material to redirect light vertically between layers with minimal loss. These components are designed to guide light efficiently in tight spaces, helping connect stacked chips without losing signal strength.
“Imagine light traveling through a chip and suddenly being redirected straight up. That’s the kind of precise control we’re achieving,” Adibi explained.
These innovations, along with advanced techniques for building vertical light paths through thick silicon layers and new packaging solutions that keep components precisely aligned, have shown promise on their own. But combining them is what enables dense, high-speed, low-loss communication between vertically stacked chips, something that no system has achieved before, according to Adibi.
“As with any complex system, success depends on how well everything is structured and optimized,” he said. “Once everything is in alignment, data can move faster, more efficiently, and with less energy consumption for communicating each bit of data.”
About the Research
This research is supported by the Defense Advanced Research Projects Agency (DARPA) Heterogeneous Adaptively Produced Photonic Interfaces (HAPPI) program. Notice ID DARPA-SN-24-105.
By combining advanced optical techniques, Professor Ali Adibi’s 3D optical routing systems looks to enable vertical chip integration in a way not previously achieved. (Photo: Allison Carter)
Wang is a recipient of the 2025 Outstanding Dissertation Award from the Association for Computing Machinery Special Interest Group on Computer-Human Interaction (ACM SIGCHI). The award recognizes Wang for his lifelong work on democratizing human-centered AI.
“Throughout my Ph.D. and industry internships, I observed a gap in existing research: there is a strong need for practical tools for applying human-centered approaches when designing AI systems,” said Wang, now a safety researcher at OpenAI.
“My work not only helps people understand AI and guide its behavior but also provides user-friendly tools that fit into existing workflows.”
[Related: Georgia Tech College of Computing Swarms to Yokohama, Japan, for CHI 2025]
Wang’s dissertation presented techniques in visual explanation and interactive guidance to align AI models with user knowledge and values. The work culminated from years of research, fellowship support, and internships.
Wang’s most influential projects formed the core of his dissertation. These included:
“I feel extremely honored and lucky to receive this award, and I am deeply grateful to many who have supported me along the way, including Polo, mentors, collaborators, and friends,” said Wang, who was advised by School of Computational Science and Engineering (CSE) Professor Polo Chau.
“This recognition also inspired me to continue striving to design and develop easy-to-use tools that help everyone to easily interact with AI systems.”
Like Wang, Chau advised Georgia Tech alumnus Fred Hohman (Ph.D. CSE 2020). Hohman won the ACM SIGCHI Outstanding Dissertation Award in 2022.
Chau’s group synthesizes machine learning (ML) and visualization techniques into scalable, interactive, and trustworthy tools. These tools increase understanding and interaction with large-scale data and ML models.
Chau is the associate director of corporate relations for the Machine Learning Center at Georgia Tech. Wang called the School of CSE his home unit while a student in the ML program under Chau.
Wang is one of five recipients of this year’s award to be presented at the 2025 Conference on Human Factors in Computing Systems (CHI 2025). The conference occurs April 25-May 1 in Yokohama, Japan.
SIGCHI is the world’s largest association of human-computer interaction professionals and practitioners. The group sponsors or co-sponsors 26 conferences, including CHI.
Wang’s outstanding dissertation award is the latest recognition of a career decorated with achievement.
Months after graduating from Georgia Tech, Forbes named Wang to its 30 Under 30 in Science for 2025 for his dissertation. Wang was one of 15 Yellow Jackets included in nine different 30 Under 30 lists and the only Georgia Tech-affiliated individual on the 30 Under 30 in Science list.
While a Georgia Tech student, Wang earned recognition from big names in business and technology. He received the Apple Scholars in AI/ML Ph.D. Fellowship in 2023 and was in the 2022 cohort of the J.P. Morgan AI Ph.D. Fellowships Program.
Along with the CHI award, Wang’s dissertation earned him awards this year at banquets across campus. The Georgia Tech chapter of Sigma Xi presented Wang with the Best Ph.D. Thesis Award. He also received the College of Computing’s Outstanding Dissertation Award.
“Georgia Tech attracts many great minds, and I’m glad that some, like Jay, chose to join our group,” Chau said. “It has been a joy to work alongside them and witness the many wonderful things they have accomplished, and with many more to come in their careers.”
]]>Wang is a recipient of the 2025 Outstanding Dissertation Award from the Association for Computing Machinery Special Interest Group on Computer-Human Interaction (ACM SIGCHI). The award recognizes Wang for his lifelong work on democratizing human-centered AI.
]]>One physicist helping lead this charge is Amira Bencherif, a postdoctoral researcher in the Epigraphene Lab at Georgia Tech, which aims to advance electronics past the limitations of silicon using graphene’s extraordinary electrical properties.
Bencherif has just been awarded a prestigious European Marie Skłodowska-Curie Action (MSCA) global post-doctoral fellowship; This year, it is expected that fewer than 20% of applicants will be selected from a record pool of over 10,000 submissions.
The highly selective fellowship will support two additional years of research at Georgia Tech with The Epigraphene Lab, followed by Bencherif working for one year at the CEA-PHELIQS Lab in Grenoble, France.
“The research in Grenoble is a critical component,” Bencherif explains. “Our Georgia Tech team brings the graphene expertise, and the CEA-PHELIQS Lab brings expertise in extreme low-temperature research. Combining these two areas will let me investigate graphene properties at extreme low temperatures, for the first time.”
The group hopes the research will lead to breakthroughs in sustainable electronics and manufacturing. “We already know that epigraphene can be used as either as a conductor or as an ultra-high mobility semiconductor,” Bencherif says. “We're still in the fundamental research phase with this new project, but combining both properties of this material on a single chip could result in very fast electronics, very small devices, and more sustainable computing.”
The fellowship builds on a longstanding partnership. “We've collaborated with our French partners on previous papers, and we have a great line of communication and trust,” shares Claire Berger, who works in the Epigraphene Lab directed by Regents' Professor Walter de Heer at Georgia Tech. “This prestigious fellowship is a recognition not only of Amira’s skills, talent and dedication as a researcher, but also of the quality of the epigraphene scientific program and the strength of the French-American collaboration.”
Berger, who serves as a professor of the practice at Georgia Tech, recently received one of France’s highest civilian honors in science and scientific diplomacy, the Chevalier dans L'ordre des Palmes Académiques. She is also the Director of Research at the French National Center for Scientific Research (CNRS) International Research Lab, which has a main presence at Georgia Tech-Europe in Metz, France, as well as a mirror site at Georgia Tech’s Atlanta campus.
“To advance this field, collaboration is crucial,” Berger says. “We cannot do it alone — the MSCA support for Amira’s work is both a testament to her hard work and the important partnership with our French counterparts.”
One key aspect of the Epigraphene Lab’s research involves developing a graphene semiconductor ten times more conductive than silicon that has the potential to create a new kind of electronics.
“Complementing its semiconducting property, some form of epigraphene has special pathways which make electronic mobility extremely high,” Bencherif explains. “This has benefits like less energy dissipation, which is important for addressing global warming and energy challenges. We use epigraphene — which is graphene grown on a silicon carbide substrate — to make electrical devices and study their electrical properties.”
“We also suspect we can use another mode of communication with current, based on the wave quantum nature of the electron, leading to coherent electronics,” which Berger shares is a long-term research project the group is pursuing.
“This type of work is very prospective and ambitious, which is why Amira was granted this prestigious fellowship,” Berger adds. “This type of research is a lot of hard work. To drive this work forward, Amira has put in an astonishing number of hours and a lot of thoughtful effort. She's incredibly creative, and it's an honor to work with her.”
]]>Contact: Jess Hunt-Ralston
]]>The project, led by the Texas Institute for Electronics (TIE) at The University of Texas at Austin, represents a total investment of $1.4 billion. The $840 million award from DARPA, announced by TIE in 2024, aims to develop the next generation of high-performing semiconductor microsystems for the Department of Defense (DoD).
“We are honored to collaborate with TIE and its broader team on this far reaching and strategic program to enable best in class 3D heterogeneous integration (3DHI) processes and technologies in the United States,” said Muhannad S. Bakir, the Dan Fielder Professor in the School of Electrical and Computer Engineering and director of the 3D Systems Packaging Research Center, who is heading the project for Georgia Tech.
3DHI is a semiconductor manufacturing process that incorporates different materials and components into microsystems with precision assembly. The use of 3DHI allows for the creation of high-performance, compact, and energy-efficient systems.
The investment is part of DARPA’s Next Generation Microelectronics Manufacturing (NGMM) Program comprised of 32 defense electronics and leading commercial semiconductor companies and 18 nationally recognized academic institutions.
Under the agreement, TIE will establish a national open access R&D and prototyping fabrication facility. The facility will enable the DoD to create higher performance, lower power, lightweight, and compact defense systems. The advancements are expected to have wide-ranging applications, including radar, satellite imaging, and unmanned aerial vehicles.
Georgia Tech will provide a wide range of expertise in 3DHI including design, fabrication and assembly processes, and characterization to support the NGMM national open-access R&D and prototyping facility at TIE.
Regents' Professor and Morris M. Bryan, Jr. Professor Suresh K. Sitaraman in the George W. Woodruff School of Mechanical Engineering will be a key contributor to Georgia Tech’s efforts on the project.
“We are delighted to be partnering with UT/TIE on the establishment of a 3D Heterogeneous Integration Microsystem prototyping facility,” said Sitaraman. “In addition to advancing fundamental science, this project is a great opportunity for Georgia Tech to demonstrate and integrate our ground-breaking and innovative 3DHI research approaches and technology solutions into TIE’s prototyping facility, and understand the challenges involved when translating lab-scale research work to a large industry-strength fabrication facility.”
ECE Professors Saibal Mukhopadhyay, Arijit Raychowdhury, Visvesh Sathe, and Shimeng Yu will be working alongside Bakir and Sitaraman.
A significant portion of the research will be conducted at the Institute for Matter and Systems (IMS), which operates Georgia Tech’s state-of-the-art electronics and nanotechnology core facilities.
Read the press release from TIE and view the project’s team and partners.
]]>Middlemen get a bad rap for adding cost and complications to an operation. So, eliminating the go-betweens can reduce expense and simplify a process, increasing efficiency and consumer happiness.
James Dahlman and his research team have been thinking along those same lines for stem cell treatments. They’ve created a technique that eliminates noisome middlemen and could lead to new, less-invasive treatments for blood disorders and genetic diseases. It sidesteps the discomfort and risks of current treatments, making life easier for patients.
“This would be an alternative to invasive hematopoietic stem cell therapies — we could just give you an IV drip,” said Dahlman, McCamish Early Career Professor in the Wallace H. Coulter Department of Biomedical Engineering. “It simplifies the process and reduces the risks to patients. That’s why this work is important.”
Dahlman and a team of investigators from Georgia Tech, Emory University, and the University of California, Davis, published their approach in the journal Nature Biotechnology.
Hematopoietic stem cells (HSCs) are like parent cells. Residing in the bone marrow, they produce all types of cells needed to sustain the blood and immune systems. Their versatility makes HSCs a valuable therapeutic tool in treating genetic blood diseases, such as sickle cell anemia, immune deficiencies, and some cancers.
HSC therapies usually involve extracting cells from the patient’s bone marrow and re-engineering them in a lab. Meanwhile, the patient endures chemotherapy to help prepare their body to receive the modified HSCs.
“These therapies are effective but also hard on the patients,” Dahlman said. “Patients undergo chemotherapy to wipe out their immune systems so the body will accept the therapeutic cells without a fight. The procedure can be life-threatening. We’re hoping to change that.”
HSCs can also be modified directly inside the body. The procedure uses lipid nanoparticles (LNPs) to carry genetic instructions to the stem cells. The LNPs have targeting ligands attached — molecules designed to find specific target cells. Precisely engineering them adds layers of time, complexity, and cost to the process. They are, like extraction from bone marrow and chemotherapy, another middleman.
The researchers wanted something simpler. They found it in a specific nanoparticle called LNP67.
“Unlike other nanoparticle designs, this one doesn’t require a targeting ligand,” Dahlman said. “It’s chemically simple, which means it’s easier to manufacture and opens the door to eventually scaling production, like mRNA vaccines.”
The key to LNP67’s success is its ability to dodge the liver, the body’s primary blood filter. Foreign invaders, even helpful invaders delivered through an IV as medicine, can be captured by a healthy liver.
“The liver absorbs almost everything,” Dahlman said. “But, by reducing what it captures by even as little as 10 percent, we can double delivery to other tissues where the nanoparticles and their payloads are needed.”
The researchers developed 128 unique nanoparticles, narrowing the list down to 105 LNPs that didn’t have targeting ligands. These were ultimately screened and evaluated for their performance in delivering genetic instructions (in the form of mRNA) effectively and safely.
LNP67 emerged as the best performer thanks to its stealthy design. For example, the surface is designed to repel proteins and other molecules that would mark the LNP for capture by the liver. This feature helped the particles circulate more evenly in the body and reach the HSCs.
“We achieved low-dose delivery without a target ligand, which is exciting,” Dahlman said. “This is something we’ve been working toward for years, and I’m very happy we got there.”
Citation: Hyejin Kim, Ryan Zenhausern, Kara Gentry, Liming Lian, Sebastian G. Huayamares, Afsane Radmand, David Loughrey, Ananda Podilapu, Marine Z. C. Hatit, Huanzhen Ni, Andrea Li, Aram Shajii, Hannah E. Peck, Keyi Han, Xuanwen Hua, Shu Jia, Michele Martinez, Charles Lee, Philip J. Santangelo, Alice Tarantal, James E. Dahlman. Lipid Nanoparticle Study, Nov. 2024, Nature Biotechnology.
Funding: This research was supported by the National Institutes of Health grants UL1TR002378, UH3-TR002855, U42 OD027094, and TL1DK136047; National Science Foundation grant 0923395. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of any funding agency.
Competing Interests: James Dahlman, Marine Z. C. Hatit, and Huanzhen Ni have filed a provisional patent related to this manuscript (US patent application number 63/632,354).
The Department of Commerce has granted the Semiconductor Research Corporation (SRC), its partners, and Georgia Institute of Technology $285 million to establish and operate the 18th Manufacturing USA Institute. The Semiconductor Manufacturing and Advanced Reseach with Twins (SMART USA) will focus on using digital twins to accelerate the development and deployment of microelectronics. SMART USA, with more than 150 expected partner entities representing industry, academia, and the full spectrum of supply chain design and manufacturing, will span more than 30 states and have combined funding totaling $1 billion.
This is the first-of-its-kind CHIPS Manufacturing USA Institute.
“Georgia Tech’s role in the SMART USA Institute amplifies our trailblazing chip and advanced packaging research and leverages the strengths of our interdisciplinary research institutes,” said Tim Lieuwen, interim executive vice president for Research. “We believe innovation thrives where disciplines and sectors intersect. And the SMART USA Institute will help us ensure that the benefits of our semiconductor and advanced packaging discoveries extend beyond our labs, positively impacting the economy and quality of life in Georgia and across the United States.”
The 3D Systems Packaging Research Center (PRC), directed by School of Electrical and Computer Engineering Dan Fielder Professor Muhannad Bakir, played an integral role in developing the winning proposal. Georgia Tech will be designated as the Digital Innovation Semiconductor Center (DISC) for the Southeastern U.S.
“We are honored to collaborate with SRC and their team on this new Manufacturing USA Institute. Our partnership with SRC spans more than two decades, and we are thrilled to continue this collaboration by leveraging the Institute’s wide range of semiconductor and advanced packaging expertise,” said Bakir.
Through the Institute of Matter and Systems’ core facilities, housed in the Marcus Nanotechnology Building, DISC will accelerate semiconductor and advanced packaging development.
“The awarding of the Digital Twin Manufacturing USA Institute is a culmination of more than three years of work with the Semiconductor Research Corporation and other valued team members who share a similar vision of advancing U.S. leadership in semiconductors and advanced packaging,” said George White, senior director for strategic partnerships at Georgia Tech.
“As a founding member of the SMART USA Institute, Georgia Tech values this long-standing partnership. Its industry and academic partners, including the HBCU CHIPS Network, stand ready to make significant contributions to realize the goals and objectives of the SMART USA Institute,” White added.
Georgia Tech also plans to capitalize on the supply chain and optimization strengths of the No. 1-ranked H. Milton Stewart School of Industrial and Systems Engineering (ISyE). ISyE experts will help develop supply-chain digital twins to optimize and streamline manufacturing and operational efficiencies.
David Henshall, SRC vice president of Business Development, said, “The SMART USA Institute will advance American digital twin technology and apply it to the full semiconductor supply chain, enabling rapid process optimization, predictive maintenance, and agile responses to chips supply chain disruptions. These efforts will strengthen U.S. global competitiveness, ensuring our country reaps the rewards of American innovation at scale.”
Whether it is the sound of music through your headphones or the precise control of a robotic arm, analog circuits play a crucial role in both established and future technologies.
Analog does a lot of things, but in general, it functions as the interpreter between the real world and digital devices. It transforms signals — like sound waves, voltage levels, temperature, pressure, and light intensity — into information that digital systems can understand.
As the semiconductor industry evolves, the demand for skilled analog engineers continues to grow even in this digital world.
“Analog circuits remain vital because they enable the initial data acquisition from the environment,” said Assistant Professor Shaolan Li. “That’s just the application perspective, but they are also structurally very different than digital circuits. Students need hands-on experience with real-world measurements, which are crucial for mastering analog circuits.”
To meet this demand, the Georgia Tech School of Electrical and Computer Engineering (ECE) is collaborating with Texas Instruments (TI) to launch strategic educational opportunities aimed at providing students access to industry-grade analog chip design, fabrication, and testing processes. TI is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips.
Tzu-Han Wang working on a circuit board with an analog chip connected to pattern generator instruments used to create continuous waveforms to test and analyze the performance of the chip.
]]>Now Georgia Tech bioengineer Ankur Singh and his research team have developed a method to improve this pioneering immunotherapy.
Their solution involves using nanowires to deliver therapeutic miRNA to T-cells. This new modification process retains the cells’ naïve state, which means they’ll be even better disease fighters when they’re infused back into a patient.
“By delivering miRNA in naïve T cells, we have basically prepared an infantry, ready to deploy,” Singh said. “And when these naïve cells are stimulated and activated in the presence of disease, it’s like they’ve been converted into samurais.”
Currently in adoptive T-cell therapy, the cells become stimulated and preactivated in the lab when they are modified, losing their naïve state. Singh’s new technique overcomes this limitation. The approach is described in a new study published in the journal Nature Nanotechnology.
“Naïve T-cells are more useful for immunotherapy because they have not yet been preactivated, which means they can be more easily manipulated to adopt desired therapeutic functions,” said Singh, the Carl Ring Family Professor in the Woodruff School of Mechanical Engineering and the Wallace H. Coulter Department of Biomedical Engineering.
The raw recruits of the immune system, naïve T-cells are white blood cells that haven’t been tested in battle yet. But these cellular recruits are robust, impressionable, and adaptable — ready and eager for programming.
“This process creates a well-programmed naïve T-cell ideal for enhancing immune responses against specific targets, such as tumors or pathogens,” said Singh.
The precise programming naïve T-cells receive sets the foundational stage for a more successful disease fighting future, as compared to preactivated cells.
Within the body, naïve T-cells become activated when they receive a danger signal from antigens, which are part of disease-causing pathogens, but they send a signal to T-cells that activate the immune system.
Adoptive T-cell therapy is used against aggressive diseases that overwhelm the body’s defense system. Scientists give the patient’s T-cells a therapeutic boost in the lab, loading them up with additional medicine and chemically preactivating them.
That’s when the cells lose their naïve state. When infused back into the patient, these modified T-cells are an effective infantry against disease — but they are prone to becoming exhausted. They aren’t samurai. Naïve T-cells, though, being the young, programmable recruits that they are, could be.
The question for Singh and his team was: How do we give cells that therapeutic boost without preactivating them, thereby losing that pristine, highly suggestable naïve state? Their answer: Nanowires.
Singh wanted to enhance naïve T-cells with a dose of miRNA. miRNA is a molecule that, when used as a therapeutic, works as a kind of volume knob for genes, turning their activity up or down to keep infection and cancer in check. The miRNA for this study was developed in part by the study’s co-author, Andrew Grimson of Cornell University.
“If we could find a way to forcibly enter the cells without damaging them, we could achieve our goal to deliver the miRNA into naïve T cells without preactivating them,” Singh explained.
Traditional modification in the lab involves binding immune receptors to T-cells, enabling the uptake of miRNA or any genetic material (which results in loss of the naïve state). “But nanowires do not engage receptors and thus do not activate cells, so they retain their naïve state,” Singh said.
The nanowires, silicon wafers made with specialized tools at Georgia Tech’s Institute for Electronics and Nanotechnology, form a fine needle bed. Cells are placed on the nanowires, which easily penetrate the cells and deliver their miRNA over several hours. Then the cells with miRNA are flushed out from the tops of the nanowires, activated, eventually infused back into the patient. These programmed cells can kill enemies efficiently over an extended time period.
“We believe this approach will be a real gamechanger for adoptive immunotherapies, because we now have the ability to produce T-cells with predictable fates,” says Brian Rudd, a professor of immunology at Cornell University, and co-senior author of the study with Singh.
The researchers tested their work in two separate infectious disease animal models at Cornell for this study, and Singh described the results as “a robust performance in infection control.”
In the next phase of study, the researchers will up the ante, moving from infectious disease to test their cellular super soldiers against cancer and move toward translation to the clinical setting. New funding from the Georgia Clinical & Translational Science Alliance is supporting Singh’s research.
CITATION: Kristel J. Yee Mon, Sungwoong Kim, Zhonghao Dai, Jessica D. West, Hongya Zhu5, Ritika Jain, Andrew Grimson, Brian D. Rudd, Ankur Singh. “Functionalized nanowires for miRNA-mediated therapeutic programming of naïve T cells,” Nature Nanotechnology.
FUNDING: Curci Foundation, NSF (EEC-1648035, ECCS-2025462, ECCS-1542081), NIH (5R01AI132738-06, 1R01CA266052-01, 1R01CA238745-01A1, U01CA280984-01, R01AI110613 and U01AI131348).
Ankur Singh has developed a new way of programming T cells that retains their naïve state, making them better fighters. — Photo by Jerry Grillo
Monitoring these tiny changes results in a wide range of applications — from improving navigation and natural disaster forecasting, to smarter medical imaging and detection of biomarkers of disease, gravitational wave detection, and even better quantum communication for secure data sharing.
Georgia Tech physicists are pioneering new quantum sensing platforms to aid in these efforts. The research team’s latest study, “Sensing Spin Wave Excitations by Spin Defects in Few-Layer Thick Hexagonal Boron Nitride” was published in Science Advances this week.
The research team includes School of Physics Assistant Professors Chunhui (Rita) Du and Hailong Wang (corresponding authors) alongside fellow Georgia Tech researchers Jingcheng Zhou, Mengqi Huang, Faris Al-matouq, Jiu Chang, Dziga Djugba, and Professor Zhigang Jiang and their collaborators.
The new research investigates quantum sensing by leveraging color centers — small defects within crystals (Du’s team uses diamonds and other 2D layered materials) that allow light to be absorbed and emitted, which also give the crystal unique electronic properties.
By embedding these color centers into a material called hexagonal boron nitride (hBN), the team hoped to create an extremely sensitive quantum sensor — a new resource for developing next-generation, transformative sensing devices.
For its part, hBN is particularly attractive for quantum sensing and computing because it could contain defects that can be manipulated with light — also known as "optically active spin qubits."
The quantum spin defects in hBN are also very magnetically sensitive, and allow scientists to “see” or “sense” in more detail than other conventional techniques. In addition, the sheet-like structure of hBN is compatible with ultra-sensitive tools like nanodevices, making it a particularly intriguing resource for investigation.
The team’s research has resulted in a critical breakthrough in sensing spin waves, Du says, explaining that “in this study, we were able to detect spin excitations that were simply unattainable in previous studies.”
Detecting spin waves is a fundamental component of quantum sensing, because these phenomena can travel for long distances, making them an ideal candidate for energy-efficient information control, communication, and processing.
“For the first time, we experimentally demonstrated two-dimensional van der Waals quantum sensing — using few-layer thick hBN in a real-world environment,” Du explains, underscoring the potential the material holds for precise quantum sensing. “Further research could make it possible to sense electromagnetic features at the atomic scale using color centers in thin layers of hBN.”
Du also emphasizes the collaborative nature of the research, highlighting the diverse skill sets and resources of researchers within Georgia Tech.
“Within the School of Physics, Professor Zhigang Jiang's research group provided the team with high-quality hBN crystals. Jingcheng Zhou, who is a member of both Professor Hailong Wang’s and my research teams, performed the cutting-edge quantum sensing measurements,” she says. “Many incredible students also helped with this project.”
Du is a leading scientist in the field of quantum sensing — this year, she received a new grant from the U.S. Department of Energy, along with a Sloan Research Fellowship for her pioneering work on developing state-of-the-art quantum sensing techniques for quantum information technology applications. The prestigious Sloan award recognizes researchers whose “creativity, innovation, and research accomplishments make them stand out as the next-generation of leaders in the fields.”
This work is supported by the U. S. National Science Foundation (NSF) under award No. DMR-2342569, the Air Force Office of Scientific Research under award No. FA9550-20-1-0319 and its Young Investigator Program under award No. FA9550-21-1-0125, the Office of Naval Research (ONR) under grant No. N00014-23-1-2146, NASA-REVEALS SSERVI (CAN No. NNA17BF68A), and NASA-CLEVER SSERVI (CAN No. 80NSSC23M0229).
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Contact: Jess Hunt-Raston
Director of Communications
College of Sciences at Georgia Tech
With this new knowledge, she could train and help other students with their research. At the time, Bonecutter-Leonard was a chemical engineering major with no plans to go into microelectronics. Working in the cleanroom changed that.
“I fell in love with microelectronics through exposure to the research and development work performed in the cleanroom,” she said.
What started as a student job led to her taking microelectronics classes — and eventually to a career in the field. “My work-study prepared me with hands-on technical skills I would have never learned from just being in a classroom,” she said. Now, Bonecutter-Leonard works as a microelectronics business chief engineer at defense contractor L3Harris Technologies.
Her story is one of many from the Institute for Electronics and Nanotechnology (IEN, the successor to MiRC), which has been training students from kindergarten to graduate school to be leaders in the microelectronics and nanotechnology space. The goal of IEN’s outreach is to make nanotechnology and microelectronics — such as computer chips and sensors — as accessible as any other science. Ultimately, these efforts will build up the U.S. workforce in the field, ensuring the country remains at the forefront of the technology that powers Americans’ everyday lives.
Bolstering the number of workers in the microelectronics industry is imperative to keep the U.S. globally competitive. Right now, 40% of the industry's labor force is older than 50, with practitioners aging out of their careers at a pace new talent cannot match. Additionally, heavy educational barriers to entry, including required degrees and specialized training, prevent more people from pursuing careers in the field. Without dedicated efforts, the entire sector — and the nation — will fall behind.
IEN is working to solve this pipeline problem.
“With the national semiconductor workforce aging, it is important now more than ever that we educate the next generation to move into these jobs,” said Michael Filler, IEN’s interim executive director. “IEN is proud to support the semiconductor industry by providing students with the interdisciplinary skills and hands-on technical training essential for success in this fast-paced, global field.”
Georgia Tech is uniquely positioned to lead this charge with its 28,500 square feet of academic cleanroom space, the largest in the Southeast and among the largest in the U.S. From micro-electro-mechanical systems to electronics fabrication, workers have 100 bays in which to conduct leading-edge research. These cleanrooms are also key teaching and training facilities.
IEN invites anyone from around the world, whether affiliated with the Institute or not, to become a core user of the cleanroom facilities. The center also regularly hosts short courses for external partners — academic, industry, and government — in microfabrication and soft lithography for microfluidics. Over the past three years, more than 700 people went through new-user orientation, and 193 enrolled in the short courses.
Making nanotechnology — of which microelectronics is an example — educationally accessible begins before college. Each semester, more than 800 K-12 students participate in IEN’s Introduction to Nanotechnology virtual lesson. Associate Director for Education and Outreach Mikkel Thomas begins his presentations by asking a simple question: What do you know about nanotechnology?
“About 99% of the time, they say that’s what makes Ironman’s suit work,” said Thomas. “That means they’ve learned the wrong lesson — that nanotechnology is a futuristic tech and that you have to be as smart as Tony Stark to work in the field.
“But most people interact with nanotechnology multiple times throughout their day, and they have no idea they're doing it.”
Thomas also emphasizes there is a career path for everyone, even if they don’t plan to get a traditional four-year degree. Part of IEN’s workforce development initiative is to build up the entire pipeline from industry and research lab technicians at the certificate level to postdoctoral researchers.
“It’s important for us to reach kids who don’t know what career options are available in nanotechnology,” Thomas said. “We want them to know that whatever they're interested in, there is a pathway for them.”
Sixth- through eighth-grade students sparked by this conversation can attend Chip Camp, a three-day STEM summer camp sponsored by Micron. They begin with a day at IEN to learn about thin films, magic sands, ferrofluids, and measuring their height in nanometers. The rest of the camp features hands-on visits to the Materials Characterization Facility (MCF) and the IEN cleanroom, where they can try on the white “bunny suits” technicians wear in the lab.
To further their reach, IEN’s workforce development team collaborates with teachers to bring nanotechnology into classrooms. During the summer, IEN offers the Research Experience for Teachers, a training program for public school and community college teachers to conduct nanotechnology research and learn how to incorporate it into their lessons. Middle school teachers have similar opportunities through the Nanoscience Summer Institute for Middle School Teachers.
When these students get to a university like Georgia Tech, IEN hires them for work-study jobs like the one Bonecutter-Leonard had. The hands-on cleanroom training is also vital to graduate students pursuing advanced degrees.
Katie Young earned her Ph.D. in materials science and engineering at Georgia Tech. Learning her way around the IEN cleanroom was essential for her graduate studies.
“My dissertation research involved synthesizing two-dimensional materials — only a single atom thick — for permeation barriers,” she explained. “I often used the cleanroom’s vacuum systems to synthesize and process 2D materials.” Now a research scientist at the Georgia Tech Research Institute, Young still works in the cleanroom on semiconductor device fabrication, building prototype quantum and biological sensors.
IEN opportunities are not limited to graduate research. Annually, about 150 Georgia Tech undergraduate students take microelectronics packaging and devices classes, with labs taught by IEN staff in the teaching cleanroom. These courses include Integrated Circuit Fabrication (ECE 4452), in which students learn to fabricate circuit elements, and the Science and Engineering of Microelectronic Fabrication (ChBE 4050/6050, open to graduate students as well), for students interested in semiconductor materials and fabrication.
Students don’t need to enroll at Georgia Tech to benefit from training, courses, and other opportunities. IEN’s internship program provides technical college students with training to become microelectronics technicians, either through work in the Biocleanroom or in the MCF.
IEN also participates in the National Science Foundation Research Experiences for Undergraduates (REU), which provides opportunities for students from underrepresented groups or who attend schools without similar facilities. While enrolled at another university, John Mark Page was introduced to Georgia Tech’s cleanroom through an REU.
“That was my first exposure to any facility of this kind, and it felt like I was looking at the future. Being in a facility that can fabricate devices at or near the atomic level — it was hard to fathom,” Page said. “I had never thought that participating in microelectronics and nanotechnology as a student, especially as an undergraduate, was something I could do.”
As a result of his REU, Page transferred to Georgia Tech — he will graduate this summer with a bachelor’s degree in electrical engineering. He also completed a second REU at the University of North Carolina at Chapel Hill, worked as a student assistant in the IEN cleanroom, and participated in a Vertically Integrated Project (VIP), Chip Scale Power and Energy.
“I was interested in the VIP because it allowed me to spend more time in the cleanroom, familiarizing myself with semiconductor fabrication methods and training on new fabrication equipment,” Page explained. His experiences inspired him to consider a future career in the semiconductor industry.
“It wasn’t only the 10-week experience of the REU that made a lasting impact on me,” he said. “It was also the relationships formed with the people of IEN. The staff there are exceptional representatives of Georgia Tech, and they make IEN a tremendous asset to the future of microelectronics and nanotechnology in the U.S.”
Biya Haile, an ECE Ph.D. student, had a similarly meaningful REU experience. Haile, whose research focuses on creating micro-electro-mechanical systems-based sensors (MEMS), described the REU as “immersive.”
“The REU project enabled me to study chemical micro-sensor technologies, as well as state-of-the-art additive nano-manufacturing techniques, which has contributed to my research,” he said. “I feel lucky that my academic journey has entailed developing new technologies that use nanoscience to solve big problems.”
While Haile is currently focused more on designing and testing rapid processes for fabricating MEMS-based devices, he still occasionally works in the cleanroom on fabrication. He plans to go into the microelectronics industry after graduating.
All of IEN’s training and educational offerings align with IEN’s mission to bolster and diversify the microelectronics workforce, according to George White, senior director of strategic partnerships for the Georgia Tech research enterprise. “IEN has been at the forefront of the CHIPS infrastructure buildout, particularly in the area of education and workforce development,” he noted.
IEN’s efforts impact not just Atlanta but the entire country. Georgia Tech’s leadership in microelectronics research trains the innovators and practitioners of the future everywhere and ensures that America stays at the forefront of leading-edge technology. As demand increases for microelectronics, IEN is moving to meet it.
Effective July 1, 2024, the Institute for Electronics and Nanotechnology and the Institute for Materials will evolve into the Institute for Matter and Systems (IMS). This strategic union aims to foster convergent research at Georgia Tech, focusing on the science, technology, and societal underpinnings of cutting-edge materials and devices. Eric Vogel will be the director of IMS, and Michael Filler will be the deputy director.
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As an evolution of the Institute for Materials (IMat) and the Institute for Electronics and Nanotechnology (IEN), IMS aims to enable convergent research at Georgia Tech related to the science, technology, and societal underpinnings of innovative materials and devices. Additionally, IMS seeks to integrate these innovations into systems that enhance human well-being and performance across information and communication, the built environment, and human-centric technologies that improve human health, wellness, and performance.
“Executive Vice President for Research Chaouki Abdallah and I are very excited about the launch of IMS, which positions Georgia Tech for integration of science and technology from atoms to devices, while explicitly drawing in researchers in the social sciences, design, business, and computing,” said Vice President of Interdisciplinary Research Julia Kubanek.
“IMS will ensure relevance across Georgia Tech through its newly configured Internal Advisor and Ambassador Board with representation across all six Colleges and GTRI,” she said. “Additional advisory committees representing IMS employees and facility users will ensure that we don’t sacrifice any of the research excellence for which IEN and IMat are known. With IMS I expect we will be even better positioned to tackle research problems that will have the greatest positive societal impact.”
Vogel will continue in his current position as the executive director of IMat until the launch of IMS. In addition to leading and growing IMat, Vogel is the Hightower Professor of Materials Science and Engineering at Georgia Tech’s School of Materials Science and Engineering, and he served as the IEN deputy director prior to leading IMat.
“It is an honor to be appointed executive director of the Institute for Matter and Systems, and I look forward to collaborating with the talented faculty and staff associated with it,” said Vogel. “This opportunity allows us to leverage the core competencies of IEN and IMat while extending our capabilities beyond nanotechnology and materials science. Together, we will be a hub for interdisciplinary research ranging from advanced materials to complex systems that solve global challenges.”
Georgia Tech’s IRIs facilitate collaboration between researchers and students from its six Colleges, the Georgia Tech Research Institute, national laboratories, and corporate entities to tackle critical topics of strategic significance for the Institute as well as for local, state, national, and international communities. IMS will also house and maintain the state-of-the-art Materials Characterization Facility and one of the largest academic cleanrooms in the nation, which offers a broad range of fabrication capabilities from basic discovery to prototype realization.
Before joining Georgia Tech in 2011, Vogel was an associate professor of materials science and engineering and electrical engineering at the University of Texas at Dallas. During this time, he also served as the associate director of the Texas Analog Center of Excellence and led UT Dallas’s involvement in the Southwest Academy for Nanoelectronics.
Prior to UT Dallas, he led the CMOS and Novel Devices Group and established the Nanofabrication Facility at the National Institute of Standards and Technology. Vogel holds a Ph.D. in electrical engineering from North Carolina State University and a B.S. in electrical engineering from the Pennsylvania State University. His research focuses on the development and fundamental understanding of electronic and nanomaterials and devices.
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