<![CDATA[Ph.D. Dissertation Defense - Athanasios Moschos]]>28475Title: From Ideal To Real: A Systems Perspective On Hardware Trojans Inside Processors
Committee:
Dr. Angelos Keromitis, ECE, Chair, Advisor
Dr. Fabian Monrose, ECE
Dr. Milos Prvulovic, ECE
Dr. Manos Antonakakis, ECE
Dr. Angelos Stavrou, Virginia Tech
]]> Daniela Staiculescu117920984442026-10-15 21:07:2417921711292026-10-16 17:18:4900eventModern computing systems rely on software defenses whose effectiveness ultimately depends on the integrity of the underlying processor hardware. Malicious hardware modifications, known as hardware trojans, can silently bypass these defenses and compromise the host system. Assessing their practical threat, however, requires looking beyond the malicious circuitry itself to consider operating-system behavior, hardware-software interactions, and constraints on attacker-controlled code execution. Adopting a systems-level perspective, this dissertation examines the practical operation of hardware trojans within general-purpose processors and subsequently explores their runtime detection through electromagnetic side-channel analysis. First, we introduce interrupt-resilient trigger mechanisms that enable dependable payload delivery despite non-deterministic operating-system interruptions, including context switching and multitasking. Second, we introduce a trigger mechanism that enables reliable trojan activation through runtime engines executing untrusted high-level code. This eliminates the need for attackers to possess prior arbitrary code execution, a restrictive assumption prevalent in prior work, and expands the practical threat surface to end-user devices. Finally, rather than attempting to detect trojans by isolating the minute electromagnetic emissions of their malicious circuitry, we investigate the anomalous microarchitectural activity induced by trojan-assisted software execution. We demonstrate a non-invasive, one-class classification approach that uses low-cost external sensing equipment to detect such activity at runtime, enabling hardware trojan detection on already-fabricated processors. Ultimately, the systems perspective reveals hardware trojans to be a system security problem rather than merely a circuit-level one, enabling more realistic threat assessment and new effective defenses.]]>2026-10-23T12:00:00-04:002026-10-23T14:00:00-04:002026-10-23T14:00:00-04:002026-10-23 16:00:002026-10-23 18:00:002026-10-23 18:00:002026-10-23T12:00:00-04:002026-10-23T14:00:00-04:00America/New_YorkAmerica/New_Yorkdatetime2026-10-23 12:00:002026-10-23 02:00:00America/New_YorkAmerica/New_Yorkdatetime<![CDATA[]]><![CDATA[Zoom link]]><![CDATA[Ph.D. Dissertation Defense - Hanqiu Chen]]>28475Title: Architecture, System and Tool Co-Design For Memory and Storage Efficient Machine Learning
Committee:
Dr. Callie Hao, ECE, Chair, Advisor
Dr. Divya Mahajan, ECE
Dr. Celine Lin, CS
Dr. Shuyi Pei, Samsung
Dr. Yiran Chen, Duke
Dr. Yuan Xie, Hong Kong UST
]]> Daniela Staiculescu117920997112026-10-15 21:28:3117920998192026-10-15 21:30:1900eventModern machine learning workloads place growing demands on memory capacity, storage space, and data communication. Although specialized hardware provides substantial computational capability, its benefits are often limited by redundant data movement, inefficient memory utilization, and the increasing size of models and datasets. Addressing these challenges requires coordinated optimization of how data is represented, stored, transferred, and processed. This research aims to enable memory- and storage-efficient machine learning through architecture, system, and tool co-design—developing efficient hardware architectures, extending these principles to resource management across multiple devices, and creating tools that simplify the development of reusable hardware.]]>2026-11-10T11:00:00-05:002026-11-10T13:00:00-05:002026-11-10T13:00:00-05:002026-11-10 16:00:002026-11-10 18:00:002026-11-10 18:00:002026-11-10T11:00:00-05:002026-11-10T13:00:00-05:00America/New_YorkAmerica/New_Yorkdatetime2026-11-10 11:00:002026-11-10 01:00:00America/New_YorkAmerica/New_Yorkdatetime<![CDATA[]]><![CDATA[Zoom link]]><![CDATA[Ph.D. Dissertation Defense - Zachary Ellis]]>28475Title: Application of Statistical Models to Secure Circuits for Improved Monitoring and Protection Against Side-Channel Attacks
Committee:
Dr. Arijit Raychowdhury, ECE, Chair, Advisor
Dr. Visvesh Sathe, ECE
Dr. Saibal Mukhopadhyay, ECE
Dr. Sanu Matthew, Intel
Dr. Anand Raghunathan, Purdue
]]> Daniela Staiculescu117920995452026-10-15 21:25:4517920996162026-10-15 21:26:5600eventLike in many disciplines of engineering and the sciences, advancement in hardware security and physical attack resistance is often carried out both through theoretical reasoning and empirical measurement representing the diverse backgrounds of hardware security researchers. The objective of this research is to leverage the work of these scholars for the advancement of circuit techniques both for attack modeling and side-channel countermeasure implementation. These methods shall uphold the levels of security required for real world use and are informed by rigorous analysis of the underlining causes of side-channel leakage. Through both implemented hardware and pre-silicon analysis tools, a comprehensive coverage of attack prevention methodologies will be presented.]]>2026-10-28T11:00:00-04:002026-10-28T13:00:00-04:002026-10-28T13:00:00-04:002026-10-28 15:00:002026-10-28 17:00:002026-10-28 17:00:002026-10-28T11:00:00-04:002026-10-28T13:00:00-04:00America/New_YorkAmerica/New_Yorkdatetime2026-10-28 11:00:002026-10-28 01:00:00America/New_YorkAmerica/New_Yorkdatetime<![CDATA[]]><![CDATA[Microsoft Teams Link ]]>