<![CDATA[Ph.D. Proposal Oral Exam - Eknath Sarkar]]> 28475 Title:  Performance and Reliability Boosters of BEOL Oxide Semiconductor Transistors for Monolithic 3D Memory and Compute

Committee: 

Dr. Datta, Advisor 

Dr. Yu, Chair

Dr. Khan

]]> Daniela Staiculescu 1 1790331501 2026-09-25 10:18:21 1790331569 2026-09-25 10:19:29 0 0 event The objective of the proposed research is to develop oxide semiconductor transistors and gate stacks that enable reliable, dense memory and compute integration within the limited thermal budget of monolithic three-dimensional systems. The work addresses the coupled tradeoffs among threshold voltage, drive current, and bias stability through device architecture and gate-stack engineering. Completed studies demonstrate tungsten-doped indium oxide nanosheet transistors with gate-all-around control, improved performance and stability using HfO₂/ZrO₂/HfO₂ (HZH) gate stacks, and four-tier ferroelectric memory operation at 125 °C. Complementary studies examine HZH reliability in silicon FinFETs and ferroelectric transistor arrays for analog in-memory computing. Building on these results, the remaining research will establish practical contacted gate pitch scaling strategies for InOₓ, IWO, and IGO transistors by jointly reducing channel and contact lengths in structures with repeated gates and source/drain contacts. A second direction will combine HZH with SiO₂ interlayer treatments, including radical processing and high-pressure annealing, to develop a reliable low-temperature CMOS gate stack for sequential complementary FET integration. Electrical and reliability measurements will identify scaling limits and process conditions that preserve transistor performance while protecting previously fabricated device tiers. These studies aim to establish experimentally supported design guidelines for vertically integrated memory and future logic technologies.

]]> 2026-09-30T14:00:00-04:00 2026-09-30T16:00:00-04:00 2026-09-30T16:00:00-04:00 2026-09-30 18:00:00 2026-09-30 20:00:00 2026-09-30 20:00:00 2026-09-30T14:00:00-04:00 2026-09-30T16:00:00-04:00 America/New_York America/New_York datetime 2026-09-30 02:00:00 2026-09-30 04:00:00 America/New_York America/New_York datetime <![CDATA[]]> <![CDATA[Microsoft Teams Meeting link]]> <![CDATA[Ph.D. Dissertation Defense - Jeremiah Lightner]]> 28475 Title:  Lightning-Based Passive Radar

Committee:

Dr. Morris Cohen, ECE, Chair, Advisor

Dr. Gregory Durgin, ECE

Dr. Aaron Lanterman, ECE

Dr. Andrew Peterson, ECE`

Dr. Joel Johnson, OSU

]]> Daniela Staiculescu 1 1790331133 2026-09-25 10:12:13 1790331157 2026-09-25 10:12:37 0 0 event Although lightning is a well-studied phenomenon, only recently have lightning tracking systems, like the the National Lightning Detection Network (NLDN) and the Lightning Mapping Array (LMA), given us precise timing and position of lightning strokes. Lightning produces high power, broadband, impulsive emissions originating from locations unsuitable for conventional Transmitter(s) (Tx) deployments. Leveraging these emissions as a Tx, we can form a passive RAdio frequency Detection And Ranging (Radar) system to monitor maritime traffic. This work evaluates the feasibility of such a system through real and simulated experiments. These experiments showed when, where, and how such a system would work. Were such a system built, it would significantly reduce the hardware needed to monitor maritime traffic, limit spectrum pollution, and increase the surveillance area for a very small cost.

]]> 2026-10-02T11:00:00-04:00 2026-10-02T13:00:00-04:00 2026-10-02T13:00:00-04:00 2026-10-02 15:00:00 2026-10-02 17:00:00 2026-10-02 17:00:00 2026-10-02T11:00:00-04:00 2026-10-02T13:00:00-04:00 America/New_York America/New_York datetime 2026-10-02 11:00:00 2026-10-02 01:00:00 America/New_York America/New_York datetime <![CDATA[]]> <![CDATA[Ph.D. Proposal Oral Exam - Lance Fernandes]]> 28475 Title:  Material and Device Engineering of Ferroelectric NAND Flash Memory for Reliable High-Density Storage

Committee: 

Dr. Khan, Advisor 

Dr. Yu, Chair

Dr. Garten

]]> Daniela Staiculescu 1 1788013067 2026-08-29 14:17:47 1788102812 2026-08-30 15:13:32 0 0 event The objective of the proposed research is to investigate scalable ferroelectric NAND (FE-NAND) memory architectures, with emphasis on device design and gate-stack engineering for memory-window (MW) optimization, retention, and pass-disturb reliability in silicon and oxide-semiconductor-channel devices. Gate stack engineering showed that Al2O3 dielectric is most effective as a tunnel dielectric layer (between two ferroelectric layers), while SiO2 performs best as a gate-blocking layer (between gate and ferroelectric layer). Combining both in a hybrid stack achieved an MW exceeding 11 V, highlighting the importance of dielectric material and placement. Channel-side interlayer studies further showed that SiO2 channel-IL provides approximately 15% higher MW, 5% lower retention loss, and 44% lower pass disturb than higher-k Al2O3 and HfO2, primarily due to reduced trap density. Finally, oxide-semiconductor-channel devices achieved approximately 1.5x larger MW than comparable silicon-channel devices but exhibited significant retention degradation from ambient oxygen interaction. Channel capping effectively suppressed this degradation and restored retention comparable to silicon devices, revealing an additional ambient-induced reliability mechanism unique to oxide-semiconductor FE-NAND

]]> 2026-09-29T14:30:00-04:00 2026-09-29T16:30:00-04:00 2026-09-29T16:30:00-04:00 2026-09-29 18:30:00 2026-09-29 20:30:00 2026-09-29 20:30:00 2026-09-29T14:30:00-04:00 2026-09-29T16:30:00-04:00 America/New_York America/New_York datetime 2026-09-29 02:30:00 2026-09-29 04:30:00 America/New_York America/New_York datetime <![CDATA[]]> <![CDATA[Microsoft Teams Meeting link]]>