Ph.D. Thesis Proposal

Sriseshan Srikanth

Ph.D. Student

School of Computer Science

College of Computing

Georgia Institute of Technology

Date: Wednesday, May 30, 2018

Time: 10 AM to 12 PM EDT

Location: KACB 1212

Committee:

Dr. Thomas M. Conte, Advisor, School of Computer Science Dr. Hyesoon Kim, School of Computer Science Dr. Milos Prvulovic, School of Computer Science Dr. Sudhakar Yalamanchili, School of Electrical and Computer Engineering Dr. Erik P. DeBenedictis, Sandia National Laboratories

Abstract:

The rate of improvement in single thread performance has reduced significantly over the last decade, due to two fundamental bottlenecks, commonly known as the power wall and the memory wall. This thesis proposes energy efficient architectues to tackle both of these issues.

Next generation devices are fast switching even at few tens of millivolts, but as a result, are vulnerable to thermal noise perturbations, resulting in intermittent, stochastic, bit errors in logic. The first part of this thesis proposes a novel, energy-efficient architecture that uses residue codes for computational error correction, in spite of the fact that residue codes cause memory access irregularities.

Another cause of memory access irregularities is sparse data applications, even when conventional architectures are used. With the help of novel representations, algorithms and near memory processing, the second part of this thesis tackles the fundamental problem of latency of main memory accesses of sparse data streams, while also significantly reducing overheads of data movement through the memory hierarchy.