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  <title><![CDATA[PhD Proposal by Pranith Denthumdas]]></title>
  <body><![CDATA[<p>Title: Efficient Consistency in Emerging Systems and Architectures<br />
<br />
Pranith Kumar<br />
School of Computer Science<br />
College of Computing<br />
Georgia Institute of Technology<br />
<br />
Data: Wednesday, January 24, 2018<br />
Time: 11:30 AM to 1:00 PM EST<br />
Location: KACB 1202<br />
<br />
Committee<br />
---------<br />
<br />
Dr. Hyesoon Kim (Advisor), School of Computer Science, Georgia Institute of Technology<br />
Dr. Milos Prvulovic, School of Computer Science, Georgia Institute of Technology<br />
Dr. Santosh Pande, School of Computer Science, Georgia Institute of Technology<br />
<br />
Abstract<br />
--------<br />
<br />
With the improvements in single core performance and processor clocks reaching<br />
a plateau, diverse systems and architectures are being explored to keep pace<br />
with Moore&rsquo;s law. The different kinds of parallel processors being explored<br />
are homogeneous, heterogeneous, and discrete offload-able systems. The most<br />
common type processing systems is where the individual processors share<br />
a single address space. One main challenge in parallel processing<br />
architectures is ensuring memory consistency without sacrificing performance.<br />
<br />
In this dissertation, we focus on reducing the overhead of memory consistency<br />
in such parallel processing systems. Our first focus is on traditional<br />
multi-core processors that implement the Release Consistency memory model<br />
where we propose to use versions to reduce the consistency overhead. Next, we<br />
work on near-data processing systems to identify bottlenecks and propose both<br />
software and hardware techniques to reduce the consistency overhead. Finally,<br />
we study cross-ISA virtual machines that when used for emulating strong memory<br />
model architectures on weak architectures (x86 on ARM) and identify<br />
overheads. We propose both software and hardware techniques to reduce this<br />
overhead.</p>

<p>&nbsp;</p>
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