{"601110":{"#nid":"601110","#data":{"type":"event","title":"PhD Proposal by Pranith Denthumdas","body":[{"value":"\u003Cp\u003ETitle: Efficient Consistency in Emerging Systems and Architectures\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nPranith Kumar\u003Cbr \/\u003E\r\nSchool of Computer Science\u003Cbr \/\u003E\r\nCollege of Computing\u003Cbr \/\u003E\r\nGeorgia Institute of Technology\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nData: Wednesday, January 24, 2018\u003Cbr \/\u003E\r\nTime: 11:30 AM to 1:00 PM EST\u003Cbr \/\u003E\r\nLocation: KACB 1202\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nCommittee\u003Cbr \/\u003E\r\n---------\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nDr. Hyesoon Kim (Advisor), School of Computer Science, Georgia Institute of Technology\u003Cbr \/\u003E\r\nDr. Milos Prvulovic, School of Computer Science, Georgia Institute of Technology\u003Cbr \/\u003E\r\nDr. Santosh Pande, School of Computer Science, Georgia Institute of Technology\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nAbstract\u003Cbr \/\u003E\r\n--------\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nWith the improvements in single core performance and processor clocks reaching\u003Cbr \/\u003E\r\na plateau, diverse systems and architectures are being explored to keep pace\u003Cbr \/\u003E\r\nwith Moore\u0026rsquo;s law. The different kinds of parallel processors being explored\u003Cbr \/\u003E\r\nare homogeneous, heterogeneous, and discrete offload-able systems. The most\u003Cbr \/\u003E\r\ncommon type processing systems is where the individual processors share\u003Cbr \/\u003E\r\na single address space. One main challenge in parallel processing\u003Cbr \/\u003E\r\narchitectures is ensuring memory consistency without sacrificing performance.\u003Cbr \/\u003E\r\n\u003Cbr \/\u003E\r\nIn this dissertation, we focus on reducing the overhead of memory consistency\u003Cbr \/\u003E\r\nin such parallel processing systems. Our first focus is on traditional\u003Cbr \/\u003E\r\nmulti-core processors that implement the Release Consistency memory model\u003Cbr \/\u003E\r\nwhere we propose to use versions to reduce the consistency overhead. Next, we\u003Cbr \/\u003E\r\nwork on near-data processing systems to identify bottlenecks and propose both\u003Cbr \/\u003E\r\nsoftware and hardware techniques to reduce the consistency overhead. Finally,\u003Cbr \/\u003E\r\nwe study cross-ISA virtual machines that when used for emulating strong memory\u003Cbr \/\u003E\r\nmodel architectures on weak architectures (x86 on ARM) and identify\u003Cbr \/\u003E\r\noverheads. We propose both software and hardware techniques to reduce this\u003Cbr \/\u003E\r\noverhead.\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Efficient Consistency in Emerging Systems and Architectures"}],"uid":"27707","created_gmt":"2018-01-22 13:33:52","changed_gmt":"2018-01-22 13:33:52","author":"Tatianna Richardson","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2018-01-24T11:30:00-05:00","event_time_end":"2018-01-24T13:00:00-05:00","event_time_end_last":"2018-01-24T13:00:00-05:00","gmt_time_start":"2018-01-24 16:30:00","gmt_time_end":"2018-01-24 18:00:00","gmt_time_end_last":"2018-01-24 18:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"221981","name":"Graduate Studies"}],"categories":[],"keywords":[{"id":"102851","name":"Phd proposal"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78761","name":"Faculty\/Staff"},{"id":"78771","name":"Public"},{"id":"174045","name":"Graduate students"},{"id":"78751","name":"Undergraduate students"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}