Committee:

Dr. Rao Tummala, ECE, Chair , Advisor

Dr. Andrew Peterson, ECE

Dr. Suresh Sitaraman, ME

Dr. Venkatesh Sundaram, PRC

Dr. Oliver Brand, ECE

Abstract:

The 2.5-D glass interposer package designed in this thesis offers the best combination of low-loss, fine-pitch interconnects and panel-scalable, double-sided fabrication processes to improve signal integrity and to reduce packaging cost compared to wafer-based silicon interposers. Specifically, this thesis addressed two major glass interposer electrical design challenges: (1) high density, die-to-die (wide I/O) interconnects with lower latency than BEOL silicon interconnects, and (2) high speed, die-to-board (external I/O) interconnects with lower attenuation than through silicon via.

Modeling, design, fabrication, and characterization of 2.5-D glass interposer RDL demonstrated a 2x reduction in wide I/O latency and a 10x reduction in external I/O attenuation compared to BEOL RDL. This electrical design research was used as a design guideline in the first 2.5-D glass interposer demonstration that integrated RDL and chip assembly processes developed by other researchers to achieve 6 μm pitch RDL and 56 μm chip-level interconnect pitch fabricated on a 100 μm thick 150 mm x 150 mm glass panel with through package via.