{"593570":{"#nid":"593570","#data":{"type":"event","title":"Ph.D. Dissertation Defense - Brett Sawyer","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle\u003C\/strong\u003E\u003Cem\u003E:\u0026nbsp; \u003C\/em\u003E\u003Cem\u003EModeling, Design and Demonstration of 2.5-D Glass Interposer Packages for High Performance Computing Applications\u003C\/em\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee:\u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Rao Tummala, ECE, Chair , Advisor\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Andrew Peterson, ECE\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Suresh Sitaraman, ME\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Venkatesh\u0026nbsp;Sundaram, PRC\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Oliver Brand, ECE\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract: \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe 2.5-D glass interposer package designed in this thesis offers the best combination of low-loss, fine-pitch interconnects and panel-scalable, double-sided fabrication processes to improve signal integrity and to reduce packaging cost compared to wafer-based silicon interposers. Specifically, this thesis addressed two major glass interposer electrical design challenges: (1) high density, die-to-die (wide I\/O) interconnects with lower latency than BEOL silicon interconnects, and (2) high speed, die-to-board (external I\/O) interconnects with lower attenuation than through silicon via.\u003C\/p\u003E\r\n\r\n\u003Cp\u003EModeling, design, fabrication, and characterization of 2.5-D glass interposer RDL demonstrated a 2x reduction in wide I\/O latency and a 10x reduction in external I\/O attenuation compared to BEOL RDL. This electrical design research was used as a design guideline in the first 2.5-D glass interposer demonstration that integrated RDL and chip assembly processes developed by other researchers to achieve 6 \u0026mu;m pitch RDL and 56 \u0026mu;m chip-level interconnect pitch fabricated on a 100 \u0026mu;m thick 150 mm x 150 mm glass panel with through package via.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Modeling, Design and Demonstration of 2.5-D Glass Interposer Packages for High Performance Computing Applications "}],"uid":"28475","created_gmt":"2017-07-18 21:02:20","changed_gmt":"2017-07-18 21:02:20","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2017-08-01T14:00:00-04:00","event_time_end":"2017-08-01T16:00:00-04:00","event_time_end_last":"2017-08-01T16:00:00-04:00","gmt_time_start":"2017-08-01 18:00:00","gmt_time_end":"2017-08-01 20:00:00","gmt_time_end_last":"2017-08-01 20:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434381","name":"ECE Ph.D. Dissertation Defenses"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}