Committee: 

Dr. Naeemi, Advisor     

Dr. Davis, Chair

Dr. Bakir

Abstract:

The objective of this research is to evaluate an interconnect design paradigm to best serve the state-of-the-art transistor technology innovations for optimal circuit performance, and power metrics. The study of the impact of technology scaling beyond the 22-nm technology node for high-speed applications has demonstrated the importance in the role of interconnect parasitics in circuit optimization, in particular, the interconnect resistance. This is validated at a physical-design level, providing analysis with a reasonably high accuracy. This work includes the analysis of the impact of interconnect fabrication methodologies on circuit performance, and proposes an optimal interconnect patterning regime for improved variability-resistance. The study is extended to futuristic devices, and devices suited for low power applications. In particular, the Tunnel-FET (TFET) device architecture is evaluated, and it is found that the highly resistive device increases the importance of wire capacitance over wire resistance, which is contrasting to the high-performance devices. This creates an opportunity to evaluate highly resistive futuristic devices against the conventional transistors, due to their lower emphasis on wire resistance with dimensional scaling.