{"590587":{"#nid":"590587","#data":{"type":"event","title":"Ph.D. Proposal Oral Exam - Divya Madapusi Srinivas Prasad","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle:\u0026nbsp; \u003C\/strong\u003E\u003Cem\u003EInterconnect Design Paradigm for Evolutionary, and Revolutionary Transistor Technologies\u003C\/em\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003ECommittee:\u0026nbsp; \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Naeemi, Advisor\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u0026nbsp;\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Davis, Chair\u003C\/p\u003E\r\n\r\n\u003Cp\u003EDr. Bakir\u003C\/p\u003E\r\n\r\n\u003Cp\u003E\u003Cstrong\u003EAbstract: \u003C\/strong\u003E\u003C\/p\u003E\r\n\r\n\u003Cp\u003EThe objective of this research is to evaluate an interconnect design paradigm to best serve the state-of-the-art transistor technology innovations for optimal circuit performance, and power metrics. The study of the impact of technology scaling beyond the 22-nm technology node for high-speed applications has demonstrated the importance in the role of interconnect parasitics in circuit optimization, in particular, the interconnect resistance. This is validated at a physical-design level, providing analysis with a reasonably high accuracy. This work includes the analysis of the impact of interconnect fabrication methodologies on circuit performance, and proposes an optimal interconnect patterning regime for improved variability-resistance. The study is extended to futuristic devices, and devices suited for low power applications. In particular, the Tunnel-FET (TFET) device architecture is evaluated, and it is found that the highly resistive device increases the importance of wire capacitance over wire resistance, which is contrasting to the high-performance devices. This creates an opportunity to evaluate highly resistive futuristic devices against the conventional transistors, due to their lower emphasis on wire resistance with dimensional scaling.\u003C\/p\u003E\r\n","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Interconnect Design Paradigm for Evolutionary, and Revolutionary Transistor Technologies"}],"uid":"28475","created_gmt":"2017-04-18 18:55:46","changed_gmt":"2017-04-18 18:55:46","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2017-04-26T12:00:00-04:00","event_time_end":"2017-04-26T14:00:00-04:00","event_time_end_last":"2017-04-26T14:00:00-04:00","gmt_time_start":"2017-04-26 16:00:00","gmt_time_end":"2017-04-26 18:00:00","gmt_time_end_last":"2017-04-26 18:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"434371","name":"ECE Ph.D. Proposal Oral Exams"}],"categories":[],"keywords":[{"id":"102851","name":"Phd proposal"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}