Committee:

Dr. Muhannad Bakir, ECE, Chair , Advisor

Dr. Gary May, ECE, Co-Advisor

Dr. Oliver Brand, ECE

Dr. Azad Naeemi, ECE

Dr. Hua Wang, ECE

Dr. Yogendra Josi, ME

Abstract:

In this research, the impact of through silicon vias (TSVs) on electrical performance of 3D/2.5D IC was experimentally investigated. It was found the delay of the 3D IC link can be improved by up 17.4% by decreasing the distance between the driver and the TSV. To address the thermal challenges, embedded microfluidic cooling heatsink testbeds were fabricated and characterized. The maximum heat transfer coefficient was up to 60 kW/m2K. A heterogeneous interconnect stitching technology (HIST) platform was proposed to conquer the shortcomings of the conventional heterogeneous integration technologies. The insertion loss of a HIST channel was 0.85 dB/mm at 50 GHz. The measured inductance and capacitance values of the compressible microinterconnects (CMIs) are approximately 50 pH and 80 fF and can be decreased via scaling.