Committee:

Dr. Moinuddin Qureshi, ECE, Chair , Advisor

Dr. Sudhakar Yalamanchili

Dr. Hyesoon Kim, CoC

Dr. Tushar Krishna, ECE

Dr. Aamer Jaleel, NVIDIA

Abstract:

In past decades, processors have incorporated more and more compute power and demanded higher memory bandwidth. As recent packaging advancement enables high-bandwidth 3D-stacked dynamic random access memory (DRAM), 3D-DRAM and high-capacity memory form a heterogeneous memory system. However, managing such systems with conventional management techniques that are developed for small on-chip caches or non-uniform-memory-access systems delivers sub-optimal performance. This dissertation investigates the problem of architecting a high-performance heterogeneous memory system and proposes simple architectural innovations that address the challenge of the hardware management of 3D-DRAM and the resource utilization and the scalability of the system.