Krishna and his coauthors will receive the top honor in the Design Methods and Tools Track for their paper, “Automatic Place-and-Route of emerging LED-driven wires within a monolithically-integrated CMOS+III-V process.” His coauthors are Arya Balachandran, Siau Ben Chiah, and Cong Wang from Nanyang Technological University (Singapore); Li Zhang, Bing Wang, Kenneth Lee Eng Kian, and Jurgen Michel from the Singapore-MIT Alliance for Research and Technology; and Li-Shiuan Peh from the National University of Singapore. 

The diminishing returns from scaling of on-chip electrical interconnects compared to logic continues to remain a challenge for chip designers, both in terms of delay and energy. This team's work makes a case for using novel μ-LED based optical interconnects as direct replacements for on-chip electrical links, both across cores and within cores in System on Chips, leveraging a monolithically integrated CMOS + III V process called LEES and measured data from InGaP LEDs. The energy consumption of μ-LED links remains the same irrespective of distance, magnifying energy savings compared to electrical links as wire lengths increase.

Working across the materials, devices, circuits, CAD, and architecture stacks, the team presents a tool flow that hides the complexity of optical devices and associated electrical circuitry behind standard cells, and automatically replaces electrical nets by LED links, subject to area constraints. The team finds that LED-interconnect based designs substantially lower energy consumption compared to electrical copper wires (~39% reduction in the Network-on-Chip, ~27% reduction within a processor core) while achieving the same latency and bandwidth, demonstrating the promise of LED on-chip interconnects as a potentially disruptive technology.