{"545161":{"#nid":"545161","#data":{"type":"event","title":"PhD Defense by Sudarsun Kannan","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle\u003C\/strong\u003E: OS Support for Heterogeneous Memory Management\u003Cbr \/\u003E \u003Cbr \/\u003E Sudarsun Kannan\u003Cbr \/\u003E School of Computer Science\u003Cbr \/\u003E College of Computing\u003Cbr \/\u003E Georgia Institute of Technology\u003Cbr \/\u003E \u003Cbr \/\u003E \u003Cstrong\u003EDate\u003C\/strong\u003E: Friday, July 1st, 2016\u003Cbr \/\u003E \u003Cstrong\u003ETime\u003C\/strong\u003E: 10 AM to 12 PM EST\u003Cbr \/\u003E \u003Cstrong\u003ELocation\u003C\/strong\u003E: KACB 3402\u003Cbr \/\u003E \u003Cbr \/\u003E \u003Cstrong\u003ECommittee\u003C\/strong\u003E:\u003Cbr \/\u003E Dr. Ada Gavrilovska (Advisor and Committee Chair, School of Computer Science, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Karsten Schwan (Advisor, School of Computer Science, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Umakishore Ramachandran (School of Computer Science, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Moinuddin Qureshi (School of Electrical and Computer Engineering, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Remzi H. Arpaci-Dusseau (Dept. of Computer Science, University of Wisconsin-Madison)\u003C\/p\u003E\u003Cp\u003EDr. Greg Eisenhauer(School of Computer Science, Georgia Tech)\u003C\/p\u003E\u003Cp\u003E\u003Cbr \/\u003E \u003Cstrong\u003EAbstract:\u003C\/strong\u003E\u003Cbr \/\u003E To address the \u0027memory wall\u0027 problem of future systems, vendors are creating heterogeneous\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ememory structures, supplementing DRAM with on-chip stacked 3D-RAM and high capacity\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Enon-volatile memory (NVM). Each of these technologies differs significantly in terms of density,\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ebandwidth, and latency. However,\u0026nbsp;current operating systems (OSes) and\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Esoftware stacks lack generic memory abstractions that can be uniformly used with different\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ememory types. This increases the software complexity\u0026nbsp;resulting in limited performance and\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Eefficiency benefits\u0026nbsp;from the memory heterogeneity for both virtualized and non-virtualized\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Esystems.\u0026nbsp;To address\u0026nbsp;these challenges, \u0026nbsp;this thesis develops HeteroMem -- an OS design\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Efor heterogeneous\u0026nbsp;memory and makes the following contribution.\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EFirst, HeteroMem introduces a unified OS abstraction for heterogeneous memories.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EAs a result, different memory technologies can extensively leverage the current advances\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Emade for traditional memory management, thereby reducing software complexity, achieving\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Eefficient use of hardware resources such as caches and TLBs, and permitting seamless\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Escaling across heterogeneous memory components. Second, HeteroMem incorporates novel\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ememory placement mechanisms focused on reducing data movement overheads. The\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Eoutcome is up to 2x improvement in application performance compared to the\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Estate-of-the-art solutions.\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EFurthermore, to exploit the persistence benefits from non-volatile memories, \u0026nbsp;HeteroMem goes\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ebeyond memory capacity scaling, to provide fast persistent object storage. Using NVMs for\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Epersistence leads to new types of cache sharing and energy bottlenecks. We address\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Ethese bottlenecks\u0026nbsp;via novel cache- and energy-efficient system software principles that do not\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Eimpact application correctness. Finally, for achieving maximum performance and reliability\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Egains with heterogeneous memory, we also explore the redesign of HPC, datacenter, and\u0026nbsp;\u003C\/p\u003E\u003Cp\u003Eend-user applications.\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E \u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"OS Support for Heterogeneous Memory Management"}],"uid":"27707","created_gmt":"2016-06-15 15:41:17","changed_gmt":"2016-10-08 02:18:03","author":"Tatianna Richardson","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2016-07-01T11:00:00-04:00","event_time_end":"2016-07-01T13:00:00-04:00","event_time_end_last":"2016-07-01T13:00:00-04:00","gmt_time_start":"2016-07-01 15:00:00","gmt_time_end":"2016-07-01 17:00:00","gmt_time_end_last":"2016-07-01 17:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"221981","name":"Graduate Studies"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}