Swaminathan shares this award with his coauthors KiJin Han, who is his former Ph.D. student and is now an assistant professor at UNIST in South Korea, and Jongwoo Jeong, who is Han’s Ph.D. student at UNIST. They will be presented with this honor at the 66th IEEE Electronic Components and Technology Conference, to be held May 31-June 3 in Las Vegas, Nevada.

The title of the award-winning paper is “Modeling of Through-Silicon Via (TSV) Interposer Considering Depletion Capacitance and Substrate Layer Thickness Effects.” Extracting the parasitics of Through Silicon Vias in 3D integrated circuits is a challenging problem. These effects are affected by the bias voltage applied to the silicon substrate and finite substrate dimensions. Hence, analytical models that have been used in the past have significant error associated with them.

In this work, Swaminathan and his colleagues use the conduction mode basis functions originally derived to model current and charge and modify them by incorporating depletion capacitance. To account for the finite substrate dimensions, multi-layered Green’s function with suitable approximations are used. The method developed has been applied to both simple examples to show accuracy and to TSV arrays to show computational efficiency.