{"508791":{"#nid":"508791","#data":{"type":"news","title":"Configurable Analog Chip Computes with 1,000 Times Less Power than Digital","body":[{"value":"\u003Cp\u003EResearchers have built and demonstrated a novel configurable computing device that uses a thousand times less electrical power \u2013 and can be built up to a hundred times smaller \u2013 than comparable digital floating-gate configurable devices currently in use.\u003C\/p\u003E\u003Cp\u003EThe new device, called the Field-Programmable Analog Array (FPAA) System-On-Chip (SoC), uses analog technology supported by digital components to achieve unprecedented power and size reductions. The researchers said that for many applications these low-power analog-based chips are likely to work as well as or better than configurable digital arrays.\u003C\/p\u003E\u003Cp\u003ECurrently, field programmable gate arrays (FPGAs) \u2013 digital devices widely used in consumer devices, defense systems and more \u2013 dominate the configurable chip market. These floating-gate integrated circuits can be altered internally at any time, and techniques to reconfigure them for many different forms and functions are well established.\u003C\/p\u003E\u003Cp\u003EProfessionals familiar with FPGAs will find the programming interface of the new analog chip surprisingly like the digital circuits in many ways, said Jennifer Hasler, a professor in the Georgia Tech School of Electrical and Computer Engineering (ECE) and leader of the research team that produced the new analog architecture.\u003C\/p\u003E\u003Cp\u003E\u201cBut in other ways the FPAA is going to seem quite different,\u201d she said. \u201cIn terms of the power needed, it\u0027s extremely different because you need only milliwatts to run the analog device, while it\u2019s hard to get an FPGA to work on less than a watt.\u201d\u003C\/p\u003E\u003Cp\u003EA paper on the new FPAA system-on-chip device has been published on the IEEE Xplore website. Another paper focusing on the details of programming FPAA devices was also published on the Xplore site. In addition a third paper, detailing a high-level open-source programming toolset developed by Hasler and her team for programming analog arrays, has also been published online in the Journal of Low Power Electronics and Applications.\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003ENovel Techniques\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003ETraditionally, analog technology has been used primarily for hard-wired circuits such as sensors that interface between digital devices and the real world; examples include the circuits that detect and reproduce sound in cell phones and other devices. Analog circuits are also used extensively in electronics to regulate and optimize power use. These single-function circuits cannot perform software-based computation, using hardware gates and switches, in the manner of digital integrated circuits.\u003C\/p\u003E\u003Cp\u003EHasler\u2019s team, however, has developed techniques that perform computation using an analog-style physical architecture by reliably positioning electrons in an FPAA\u2019s connective structure. This approach stands in contrast to FPGAs, which process electrons through floating gates in ways similar to conventional digital semiconductors such as memory chips or central processing units.\u003C\/p\u003E\u003Cp\u003EOne advantage of FPAAs is that they\u0027re non-volatile, Hasler explained, meaning they retain data even when power is turned off. This is similar to flash memory technology, such as the solid-state drives and storage cards commonplace today. The use of non-volatile memory reduces power consumption, in contrast to the higher power needs of the volatile SRAM configurations typically used in FPGAs.\u003C\/p\u003E\u003Cp\u003E\u201cIn addition to being non-volatile, our analog architecture lets us do something fairly radical \u2013 we can compute using the routing fabric of the chip, exploiting areas that are usually considered just dead weight,\u201d Hasler said. \u201cTo help do this, we\u0027ve developed highly efficient switches that can be programmed on, off, or in-between \u2013 partially on and partially off. This flexibility provides both increased computation capabilities and reduced power consumption.\u201d\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EMilliwatts or Microwatts\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EThe present FPAA device can operate on less than 30 milliwatts \u2013 thousandths of a watt, Hasler explained. That level approaches three orders of magnitude less than a conventional digital configurable chip. Further design advances in analog arrays could bring their power needs down into the microwatt range \u2013 millionths of a watt.\u003C\/p\u003E\u003Cp\u003ETo program the analog environment of the new device, researchers manipulate electrons in precise ways. Using electron-injection and electron-tunneling techniques, they erase data by lowering the number of electrons at specific locations in the device structure to the lowest possible value. Then they encode new data by increasing the number of electrons located at a given location up to an exact value.\u003C\/p\u003E\u003Cp\u003EThis complex approach makes possible a highly dense chip structure that offers many parameters \u2013 meaning programmable variables that can exist in a large number of different states and offer many shadings of behavior. It is this structural density that allows greater computing capability for a given degree of physical size and power input.\u003C\/p\u003E\u003Cp\u003E\u201cOur FPAA chip has roughly half a million of these programmable parameters,\u201d Hasler said. \u201cThey can be used as a switch in a digital manner \u2013 using the lowest possible value for \u2018off\u2019 or the highest possible value for \u2018on\u2019 \u2013 or we can achieve even more rich behavior using intermediate values.\u201d\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EA New Toolset\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EThe FPAA device includes a small amount of built-in digital circuitry that supports communication within the chip and also helps run the programming infrastructure. Utilizing these support features, the team has developed an extensive set of high-level programming tools to take advantage of the new chip.\u003C\/p\u003E\u003Cp\u003EAmong other things, the new toolset is designed to make working with analog arrays accessible to those familiar with digital designs like FPGAs, which are programmed using comparable high-level tools. The new toolset can both simulate and program the FPAA reconfigurable device. A paper detailing these high-level tools has been published online.\u003C\/p\u003E\u003Cp\u003E\u201cOur toolset uses high-level software developed in the Scilab\/Xcos open-source programs, with an analog and mixed-signal library of components,\u201d Hasler said. \u201cGeorgia Tech undergraduates are already using these tools in classes in the School of Electrical and Computer Engineering that cover mixed-signal and analog devices and tools.\u201d\u003C\/p\u003E\u003Cp\u003EOne area in which the analog approach is notably powerful involves command words \u2013 voice recognition technology used in devices like smartphones to do such things as wake up circuits from an off state, Hasler said. Like traditional analog sensing circuits, an FPAA offers excellent context-aware capability at extremely low power states.\u003C\/p\u003E\u003Cp\u003EHasler said that she has talked with several companies about potential applications of the FPAA in commercial devices. A significant number of FPAA chips has already been produced, but plans for potential large-scale manufacture of the chips have not been finalized. The key technologies in the FPAA system-on-chip are patent pending.\u003C\/p\u003E\u003Cp\u003E\u201cWe believe that analog technology offers very powerful ways to look at physical computing, with considerable potential for commercial, neuromorphic, military and other applications,\u201d Hasler said.\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003ECITATIONS\u003C\/strong\u003E:\u003C\/p\u003E\u003Cp\u003ESihwan Kim, et al., \u201cIntegrated Floating-Gate Programming Environment for System-Level ICs,\u201d (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015). \u003Ca href=\u0022http:\/\/dx.doi.org\/10.1109\/TVLSI.2015.2504118\u0022 title=\u0022http:\/\/dx.doi.org\/10.1109\/TVLSI.2015.2504118\u0022\u003Ehttp:\/\/dx.doi.org\/10.1109\/TVLSI.2015.2504118\u003C\/a\u003E\u003C\/p\u003E\u003Cp\u003ESuma George, et at., \u201cA Programmable and Configurable Mixed-Mode FPAA SoC,\u201d (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016). \u003Ca href=\u0022http:\/\/www.dx.doi.org\/10.1109\/TVLSI.2015.2504119\u0022 title=\u0022http:\/\/www.dx.doi.org\/10.1109\/TVLSI.2015.2504119\u0022\u003Ehttp:\/\/www.dx.doi.org\/10.1109\/TVLSI.2015.2504119\u003C\/a\u003E\u003C\/p\u003E\u003Cp\u003EMichelle Collins, et al., \u201cAn Open-Source Tool Set Enabling Analog-Digital-Software Co-Design,\u201d (Journal of Low-Power Electronics and Applications, 2016). \u003Ca href=\u0022http:\/\/dx.doi.org\/10.3390\/jlpea6010003\u0022 title=\u0022http:\/\/dx.doi.org\/10.3390\/jlpea6010003\u0022\u003Ehttp:\/\/dx.doi.org\/10.3390\/jlpea6010003\u003C\/a\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cbr \/\u003E\u003Cstrong\u003EResearch News\u003C\/strong\u003E\u003Cbr \/\u003E\u003Cstrong\u003EGeorgia Institute of Technology\u003C\/strong\u003E\u003Cbr \/\u003E\u003Cstrong\u003E177 North Avenue\u003C\/strong\u003E\u003Cbr \/\u003E\u003Cstrong\u003EAtlanta, Georgia 30332-0181 USA\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EMedia Relations Contact\u003C\/strong\u003E: John Toon (404-894-6986) (\u003Ca href=\u0022mailto:jtoon@gatech.edu\u0022\u003Ejtoon@gatech.edu\u003C\/a\u003E).\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EWriter\u003C\/strong\u003E: Rick Robinson\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EResearchers have built and demonstrated a novel configurable computing device that uses a thousand times less electrical power \u2013 and can be built up to a hundred times smaller \u2013 than comparable digital floating-gate configurable devices currently in use.\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"Researchers have demonstrated a novel reconfigurable computing device that uses much less power than comparable digital devices."}],"uid":"27303","created_gmt":"2016-03-02 21:41:33","changed_gmt":"2016-10-08 03:20:57","author":"John Toon","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2016-03-03T00:00:00-05:00","iso_date":"2016-03-03T00:00:00-05:00","tz":"America\/New_York"},"extras":[],"hg_media":{"508741":{"id":"508741","type":"image","title":"FPAA Chip","body":null,"created":"1457114400","gmt_created":"2016-03-04 18:00:00","changed":"1475895270","gmt_changed":"2016-10-08 02:54:30","alt":"FPAA Chip","file":{"fid":"204918","name":"fpaa-chip5.jpg","image_path":"\/sites\/default\/files\/images\/fpaa-chip5_1.jpg","image_full_path":"http:\/\/hg.gatech.edu\/\/sites\/default\/files\/images\/fpaa-chip5_1.jpg","mime":"image\/jpeg","size":1938985,"path_740":"http:\/\/hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/fpaa-chip5_1.jpg?itok=d5jOKKn7"}},"508761":{"id":"508761","type":"image","title":"FPAA System on Chip","body":null,"created":"1457114400","gmt_created":"2016-03-04 18:00:00","changed":"1475895270","gmt_changed":"2016-10-08 02:54:30","alt":"FPAA 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Chip3","file":{"fid":"204922","name":"fpaa-chip8.jpg","image_path":"\/sites\/default\/files\/images\/fpaa-chip8_0.jpg","image_full_path":"http:\/\/hg.gatech.edu\/\/sites\/default\/files\/images\/fpaa-chip8_0.jpg","mime":"image\/jpeg","size":2222969,"path_740":"http:\/\/hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/fpaa-chip8_0.jpg?itok=DKzH5oRD"}}},"media_ids":["508741","508761","508771","508781"],"groups":[{"id":"1188","name":"Research Horizons"}],"categories":[{"id":"145","name":"Engineering"},{"id":"135","name":"Research"}],"keywords":[{"id":"7569","name":"analog"},{"id":"169991","name":"FPAA"},{"id":"171780","name":"FPAA system-on-chip"},{"id":"91651","name":"Jennifer Hasler"}],"core_research_areas":[{"id":"39451","name":"Electronics and Nanotechnology"}],"news_room_topics":[{"id":"71881","name":"Science and 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