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  <title><![CDATA[Lunch and Learn: ANSYS]]></title>
  <body><![CDATA[<p>Challenges of power delivery through the board, package and on-die power delivery network require performing signal integrity and power integrity analysis. Successful engineering teams are adopting simulation and analysis-driven product design flows for IC, package and PCB power delivery network to address electrical and thermal challenges including EMI compliance and electrostatic discharge.<br />Come join us for this free lunch and learn to discover ANSYS Integrated Chip–Package–System Simulation:<br />• Discover the ANSYS chip–package–system workflow which provides chip-aware package and PCB analysis as well as package and PCB-aware chip analysis<br />• Learn about the Chip Power Model (CPM), a compact SPICE-correlated model of the full-chip power delivery network to accurately represent chip behavior for package and PCB simulation<br />• See how our 3D system-level thermal simulator is used to perform complex thermal management analysis.</p>]]></body>
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      <value><![CDATA[2016-03-10T09:30:00-05:00]]></value>
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      <value><![CDATA[<p>Madhavan Swaminathan</p><p><a href="mailto:madhavan.swaminathan@ece.gatech.edu">madhavan.swaminathan@ece.gatech.edu</a></p>]]></value>
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          <item><![CDATA[School of Electrical and Computer Engineering]]></item>
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