{"459041":{"#nid":"459041","#data":{"type":"event","title":"PhD Defense by Brian Railing","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle:\u0026nbsp;Collecting and Representing Parallel Programs with High Performance Instrumentation\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003E\u0026nbsp;\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EBrian Railing\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003ESchool of Computer Science\u003Cbr \/\u003E College of Computing\u003Cbr \/\u003E Georgia Institute of Technology\u003Cbr \/\u003E \u003Cbr \/\u003E\u003Cstrong\u003E Date:\u0026nbsp;Friday, October 30, 2015\u003C\/strong\u003E\u003Cbr \/\u003E\u003Cstrong\u003E Time:\u0026nbsp;3:00 PM \u2013 5:00 PM ET\u003C\/strong\u003E\u003Cbr \/\u003E\u003Cstrong\u003E Location: MiRC 102B\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003ECommittee:\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E---------------\u003C\/p\u003E\u003Cp\u003EDr. Thomas Conte (Advisor, School of Computer Science and School of\u0026nbsp;Electrical and Computer Engineering, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Santosh Pande\u0026nbsp;(School of Computer Science, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Richard Vuduc (School of Computational Science and Engineering, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Sudhakar Yalamanchili (School of Electrical and Computer Engineering, Georgia Tech)\u003C\/p\u003E\u003Cp\u003EDr. Bruce Worthington (Partner Computer Engineering Lead, Microsoft)\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003E\u0026nbsp;\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003EAbstract:\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003E------------\u003C\/p\u003E\u003Cp\u003E\u003Cem\u003EComputer architecture has looming challenges with finding program parallelism, process technology limits, and limited power budget.\u0026nbsp; To navigate these challenges, a deeper understanding of parallel programs is required. I will discuss the task graph representation and how it enables programmers and compiler optimizations to understand and exploit dynamic aspects of the program.\u003C\/em\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cem\u003E\u0026nbsp;\u003C\/em\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cem\u003EI will present Contech: a high performance framework for generating dynamic task graphs from arbitrary parallel programs.\u0026nbsp; The Contech framework supports a variety of languages and parallelization libraries, and has been tested on both x86 and ARM.\u0026nbsp; I will demonstrate how this framework encompasses a diversity of program analyses, particularly by modeling a dynamically reconfigurable, heterogeneous multi-core processor.\u003C\/em\u003E\u003C\/p\u003E\u003Cp\u003E \u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"Collecting and Representing Parallel Programs with High Performance Instrumentation"}],"uid":"27707","created_gmt":"2015-10-14 14:58:18","changed_gmt":"2016-10-08 02:14:21","author":"Tatianna Richardson","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2015-10-30T16:00:00-04:00","event_time_end":"2015-10-30T18:00:00-04:00","event_time_end_last":"2015-10-30T18:00:00-04:00","gmt_time_start":"2015-10-30 20:00:00","gmt_time_end":"2015-10-30 22:00:00","gmt_time_end_last":"2015-10-30 22:00:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"221981","name":"Graduate Studies"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}