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    <user id="27863"><![CDATA[27863]]></user>
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  <created>1381848302</created>
  <changed>1475893603</changed>
  <title><![CDATA[Large Silicon, Glass or Low-CTE Organic Package to Printed Wiring Board SMT Interconnections]]></title>
  <body><![CDATA[<p>Large, low-TCE packages are required in both high-performance, as 2.5D packages in sizes as large as 60 mm and with lithographic ground rules below 5 microns, as well as in consumer electronics. These low-TCE packages are also needed to avoid stress on the ultra-low k dielectrics within the chip, as they tend to be fragile. Low-TCE packages are required in modern consumer applications to minimize thickness.</p><p><a href="http://www.chipscalereview.com/tech_monthly/csrtm-0713-smt-interconnections.php">Read the entire research report at Chip Scale Review online.</a></p>]]></body>
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      <url><![CDATA[http://www.chipscalereview.com/tech_monthly/csrtm-0713-smt-interconnections.php]]></url>
      <title><![CDATA[]]></title>
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  <field_publication>
    <item>
      <value><![CDATA[ main streets ]]></value>
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  <field_dateline>
    <item>
      <value>2013-07-15</value>
      <timezone></timezone>
    </item>
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  <field_media>
        </field_media>
  <og_groups>
          <item>197261</item>
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  <og_groups_both>
          <item><![CDATA[Institute for Electronics and Nanotechnology]]></item>
      </og_groups_both>
    <field_userdata><![CDATA[]]></field_userdata>
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