Mr. Pan’s and Dr. Naeemi’s paper–entitled "Device- and System-Level Performance Modeling for Graphene P-N Junction Logic"–presents the first comprehensive performance modeling and assessment at the device-, circuit-, and system-levels for graphene pn junction switches and offers important insights into the limits and opportunities of this emerging technology.

As CMOS scaling approaches its fundamental limits, it is critical to develop novel device technologies to augment or even replace the conventional Si CMOS logic. Graphene with its unique physical and electrical properties is considered a prominent candidate for this purpose. However, graphene is a naturally gapless material and virtually all efforts in opening a gap in its bandstructure negatively affect its excellent electron transport properties. Graphene pn junction devices rely on angular dependent electron transport at the pn junctions in graphene and do not need a bandgap to operate as a switch.