Title:  Energy Efficient Processing In Memory Architecture For Deep Learning Computing Acceleration

Committee:

Dr. Saibal Mukhopadhyay, ECE, Chair , Advisor

Dr. Asif Khan, ECE

Dr. Shimeng Yu, ECE

Dr. Tushar Krishna, ECE

Dr. Hyesoon Kim, CoC

Abstract:

The major objective of this research is to make the PIM (processing-in-memory) based deep learning accelerator more practical and more computing efficient. The research first proposes an ReRAM based RNN accelerator which integrates ReRAM based processing engine for VMM computing and digital logic for element-wise operation/transcendental function together, without compromising the versatility to support the computation for other types of DNN models. Regarding the challenges stemmed from ReRAM, this research explores Ferroelectrical FET (FeFET) to replace ReRAM as the basic memory cell in PIM architecture. A dedicated data communication network, named H-NoC, is also presented in this work to enhance the data transmission efficiency. Moreover, to enable training and further enhance the computing efficiency, this research proposes an all-digital, flexible precision PIM design where the ADC/DAC are eliminated and the computation is performed with dynamical bit-precision. This research also proposes algorithmic approaches to suppress the computing accuracy deterioration caused by device variation, leading to a robust PIM engine with un-robust devices. Finally, this research presents a novel DNN model, named HybridNet, which integrates model based design and data driven learning together for dynamical system modeling. The hardware implementation of HybridNet is elaborated to show its computing efficiency.