Abstract: By leveraging the phenomena of quantum superposition and entanglement, some specifically designed quantum algorithms can achieve polynomial to exponential speed up when compared to their best classical counterparts, thus holding great promise for a variety of applications such as secure data exchange, database search, machine learning, and simulation of quantum processes. Quantum computers are envisioned as hybrid devices where quantum cores operate in conjunction with classical circuitry, part of which is dedicated to programming, control and post-processing functions.

Among several potential platforms for implementing the quantum core, electrically addressable solid-state qubits are in principle well-positioned for scaling up to the millions of qubits necessary to run useful, fault-tolerant calculations. This is especially true for Si spin qubits, which are encoded in the spin degree of freedom of one or several elementary charges, confined by MOS Gates with characteristic dimensions of only a few tens of nanometers. Their recently demonstrated compatibility with standard CMOS technology is an advantage in terms of fabricating large high-density arrays of Quantum Dots with controlled variability, but also in the perspective of seamless cointegration with the control electronics required for addressing, manipulation and readout of the qubits.

The typical energy scales between the spin states impose simultaneously i/ low temperature operation (~1K) and thus minimal dissipation; ii/ resonant transitions driven by high frequency input signals (>GHz); iii/ minimizing cross-talk in a high-density environment. Additional constraints are set by Quantum Error Correction (QEC) protocols, notably in terms of parallelized reflectometry-based sensing and data transfer management. This talk will review our latest progress in the field of few Si spin qubits experiments, and by sketching the contours of more extensible architectures, provide a glimpse of the engineering challenges to be tackled for the purpose of designing a fault tolerant universal quantum computer.

Bio: Louis Hutin received the PhD degree in electrical engineering from Grenoble INP in 2010. His research focus is device integration for CMOS and beyond CMOS digital logic. He joined the University of California, Berkeley in 2010, where he worked towards scaling nanoelectromechanical relays for ultra-low-power logic and non volatile memory. He returned in 2013 to CEALeti, primarily investigating possible implementations of quantum logic based on Si CMOS technology. Louis Hutin received the Norman Hackerman Young Author Award of the Electrochemical Society in 2009 for his work on Schottky junctions. He authored and co-authored more than 100 international communications in peer-reviewed journals and conference proceedings and holds 13 patents.