Title:  Characterization of Library Cells for Intra-cell Defect Exposure: A Systematic Methodology

Committee: 

Dr. Chatterjee, Advisor  

Dr. Mukhopadhyay, Chair

Dr. Milor

Abstract:

The objective of the proposed research is to develop methodologies, support algorithms, test generation infrastructure and characterization for testing of manufacturing defects which occur at the transistor level for standard cell libraries. In this work, a systematic approach for test generation is presented for resistive open defects. We show by exhaustive simulations, the requirement of multi-bit change and multi-pattern test patterns for detection of the resistive faults (open defects) which escape the traditional testing approach. We present the correlation observed between the algorithm and simulation results along with other useful observations from the exhaustive spice simulations for open defects. There is a significant amount of speed-up which can be achieved by using a guided simulation approach for the detection of the open resistive faults as is shown by the experimental results. In the future work, we plan to refine and generalise the test generation algorithm by including the short defects into the algorithm. Exhaustive simulation for short defects will be done for comparison of fault coverage and the algorithm efficiency. We plan to investigate fault dominance and equivalence for intra-cell defects and include them in the algorithm. We also plan to validate the approach on higher technology node libraries such as 15nm and other open source libraries. We will also explore the correlation between resistive defect sizes and the physical layout of the standard cells. The final goal of this research is to develop a generalised closed loop test generation infrastructure for characterisation and testing of intra-cell defects in standard library cells