Title:  A Multi-physics Approach to the Co-design of 3D Multicore Processors

Committee:

Dr. Sudhakar Yalamanchili, ECE, Chair , Advisor

Dr. Yogendra Joshi, ME

Dr. Saibal Mukhopadhyay, ECE

Dr. Yorai Wardi, ECE

Dr. Hyesoon Kim, CoC

Abstract:

The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a single package and enables high integration density. Compared to 2D planar design, 3D ICs shorten the die-to-die distance and substantially increase inter-die communication bandwidth, providing a potential performance boost for large-scale systems. However, the design of 3D multi-core processors exposes great challenges to computer architect. First, 3D ICs create design bottlenecks in thermal management and power delivery. Second, the strong coupling relationship between performance, power, and thermal in 3D ICs adds design complexities. These factors require a holistic view to design high-performance energy-efficient 3D processors.

The purpose of the dissertation is to promote a multi-physics co-design methodology in 3D processors that achieves performance gain and energy efficiency. Towards this goal, this dissertation explores the co-design opportunities in a 3D multi-core processor from three perspectives. The first looks into a thermal-architecture co-design, which develops two thermal-aware adaptation mechanisms in 3D processors and improves runtime energy efficiency. The second focuses on a power-architecture co-design, which minimizes the voltage guardband based on the thermal characterization in SRAM cache and architectural-level prediction for power reduction. The last works on a package-architecture co-design and proposes a thread scheduling policy for heterogeneous architecture in a 3D package to maximize system performance given a thermal cap. By evaluating the effectiveness of these approaches, the dissertation wishes to establish the value of the multi-physics co-design as an integral part of future processor design.