THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING

GEORGIA INSTITUTE OF TECHNOLOGY

Under the provisions of the regulations for the degree

DOCTOR OF PHILOSOPHY

on Tuesday, August 8, 2017

12:00 PM
in MaRC 431

will be held the

DISSERTATION DEFENSE

for

Yuya Suzuki

"Ultra-thin Polymer Dielectric Materials and Ultra-small Via and Trench Processes for 20µm Bump Pitch Re-distribution Layer (RDL) Structures for High Density Packages"

Committee Members:

Prof. Rao R. Tummala, Advisor, MSE

Prof. Eric M. Vogel, MSE

Prof. C. P. Wong, MSE

Prof. Suresh Sitaraman, ME

Dr. Venky Sundaram, ECE

Abstract:

Higher interconnect density between multiple chips is required because of the need for higher bandwidth data transmission for many electronic systems, such as smart mobile devices, cloud and edge computing, and in machine learning in autonomous driving and robotics. Although side-by-side integration with 2.5D silicon interposers with back end of line (BEOL) wafer processes have enabled the high input-output (I/O) density interconnections, they have challenges in electrical performance and cost. Meanwhile, organic package substrates have higher electrical performance and low cost capability, however, they have been unable to bridge the I/O pitch gap from 80 µm to 20 µm, because of the dimensional instability and warpage.

The objectives of this research are to explore and demonstrate ultra-thin dry film polymer materials, processes and lithographic structures to form copper-polymer re-distribution layers (RDL) with silicon wafer-like interconnection densities, but at lower resistance and at lower cost. This research is focused on addressing the limitations of current approaches by; (a) design and demonstration of a novel ultra-thin RDL dielectric material that satisfies the properties for RDL with scalability of conductor wiring to 2 µm by SAP, and (b) investigation of an innovative embedded trench process with fly-cutting planarization tool to achieve 5 µm diameter micro-vias, and 2 µm wiring traces with high positional accuracy at ±1-2 µm. Detail design of the dielectric thickness was based on the 50 ohm impedance matching calculation and thermo-mechanical finite element modeling approach. Additionally, new dielectric materials with excellent materials were introduced and in-depth analysis of their electrical, thermo-mechanical and adhesion properties were performed. To develop the RDL wiring process, a new embedded trench formation process was developed using parallel mask projection processes and an innovative planarization process to address the challenges of RDL scaling with current processes.